riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	eff659cd43	Merge pull request #2056 from binno/remove_shift_in_vstopi Don't shift enabled bits of interrupt in vstopi csrs	9 months ago
Binno	e515a8fbcd	Don't shift enabled bits of interrupt in vstopi csrs Signed-off-by: Binno <binno.shen@sifive.com>	9 months ago
Nado15	23ad840e4d	Add VLEN < ELEN validation check	9 months ago
Andrew Waterman	1553a2a896	Merge pull request #2053 from riscv-software-src/fix-2052 Support FLI.H for Zfa && Zvfh && !Zfh	9 months ago
Andrew Waterman	d0c345184f	Support FLI.H for Zfa && Zvfh && !Zfh Resolves #2052	9 months ago
Andrew Waterman	e17097aaea	Merge pull request #2051 from riscv-software-src/fix-2050 Fix regression introduced by #2050	9 months ago
Andrew Waterman	d951d9bc6a	Fix regression introduced by #2050 Don't assert SEW=8 for fp16 <> int8 conversions.	9 months ago
Andrew Waterman	5da583ee34	Merge pull request #2050 from riscv-software-src/vfp-refactor Factor out common vector FP prologue	9 months ago
Andrew Waterman	4e4d9f99ee	Factor out rounding-mode validation	9 months ago
Andrew Waterman	3c0db13b52	Factor out common vector FP prologue	9 months ago
Andrew Waterman	2dfd52759b	Merge pull request #2049 from riscv-software-src/vector-cleanup Minor vector-unit cleanup	9 months ago
Andrew Waterman	d3b3fcba82	Use class member initialization in vector unit	9 months ago
Andrew Waterman	c04d2381d1	Remove dead code in vector unit	9 months ago
Andrew Waterman	dd4d3fbca9	Implement Zvbdot draft	9 months ago
Andrew Waterman	d4568f6693	Merge pull request #2048 from hdinc/patch-1 ns16550.cc : fix handling clear rx/tx FIFO requests.	9 months ago
Andrew Waterman	737787f160	Merge pull request #2046 from ha0lyu/master fix: check ext_str size when ext = zve*	9 months ago
hdinc	d62d3075a2	ns16550.cc : fix handling clear rx/tx FIFO requests. Signed-off-by: hdinc <macellan091@gmail.com>	10 months ago
Hao	9950cb3d59	fix: check ext_str size when ext = zve* `zve` = "zve{32, 64}{x, f, d}", size of `zve` must be 6. Signed-off-by: Hao <58808837+ha0lyu@users.noreply.github.com>	10 months ago
Andrew Waterman	113ef64f67	Merge pull request #2044 from klingaard/klingaard/issue_2038_quad_logging_store_issue For writes + logging, if len > 8 bytes, break up the memory log	10 months ago
Knute Lingaard	4ecd2e7e79	Merge branch 'master' into klingaard/issue_2038_quad_logging_store_issue	10 months ago
Andrew Waterman	0fa8e0c710	Merge pull request #2040 from mmhus/mmhus/take-sireg-case-out-of-switch Sireg is not in the sireg_csrs[] list, so needs to be checked outside… #2041	10 months ago
Knute Lingaard	09e4d6d089	Fixed issues with logging	10 months ago
Muhammad Moiz Hussain	5063dcb8ea	Sireg is not in the sireg_csrs[] list, so needs to be checked outside of the switch-case	10 months ago
Andrew Waterman	2794373c62	Merge pull request #2042 from riscv-software-src/register-device Don't include built-in devices in mmio_device_map	10 months ago
Andrew Waterman	8da8b6a34d	Don't include built-in devices in mmio_device_map Only use mmio_device_map for plugin devices. This fixes a collision caused by multiple static initializers if Spike depends on a library that depends on libriscv.so.	10 months ago
Andrew Waterman	c61e4bccce	Remove brittle reliance on ordering of factory table	10 months ago
Andrew Waterman	483e01d486	Merge pull request #2037 from riscv-software-src/2036-redux Only support 56-bit PMP and ATP addresses	10 months ago
Andrew Waterman	352597c4cf	Remove MAX_PADDR_BITS It isn't used anymore.	10 months ago
Andrew Waterman	a89875689e	Only support 56-bit PMP addresses As mandated by the ISA spec.	10 months ago
Andrew Waterman	72e8cad123	Implement processor_t::paddr_bits correctly It wasn't being called anywhere, so the 50- vs. 56-bit discrepancy never manifested.	10 months ago
Andrew Waterman	94beb3c026	Remove physical address checks in sim_t Processors are responsible for validating physical addresses; the bus is only responsible for making some device lives at a given address.	10 months ago
Andrew Waterman	3e58f5ef62	Merge pull request #2033 from i2h2/vs-interrupts AIA: vstopi should only be used for AIA-extended interrupts	10 months ago
Ian Huang	b6f4d246bc	AIA: vstopi should only be used for AIA-extended interrupts VSEIP/VSTIP/VSSIP should come in through the non-SSAIA path. vstopi will be used to throw VTI and IID > 13 interrupts.	11 months ago
Andrew Waterman	2a0bb5f543	Merge pull request #2029 from theOfficeCat/README.md-zfa Add Zfa to README.md	10 months ago
Aike Gilabert Gámez	b9e1d219c8	Add Zfa to README.md Signed-off-by: Aike Gilabert Gámez <aikegilabert@gmail.com>	10 months ago
Andrew Waterman	965547260a	Merge pull request #2025 from mslijepc/mslijepc_20250702_additional-files-riscvmkin added jtag_dtm and remote_bitbang to riscv_install_hdrs	11 months ago
Andrew Waterman	4c932cff7a	Merge pull request #1882 from fk-sc/fk-sc/mprven-support Add DCSR.MPRVEN support	11 months ago
mslijepc	d2cf8b0419	added jtag_dtm and remote_bitbang to riscv_install_hdrs	11 months ago
Farid Khaydari	9b2a1d6c81	Add DCSR.MPRVEN support Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status). This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2). This change: * Increases debug specification coverage, allows more detailed testing of external debuggers with Spike. * Decreases the number of required abstract commands to read virtual memory thus improving the user experience. Commit's changes: * Added MPRVEN field to DCSR register * Updated debug_rom.S to turn off MPRVEN on memory access To avoid unwanted address translation while debug_rom.S executed DCSR.MPRVEN bit has to be cleared before and restored after access. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>	1 year ago
Andrew Waterman	ba54a6015f	Merge pull request #2022 from aap-sc/aap-sc/another_unused_variable_warning remove unused EGS constant from vsm4r_vs handler	11 months ago
Parshintsev Anatoly	7f8aa45514	remove unused EGS constant from vsm4r_vs handler The macro require_vsm4_constraints defines EGS once again (shadowing the definition of this constant, since it introduces a new scope). This renders the original definition as "unused", causing warning during compilation.	11 months ago
Andrew Waterman	14670706c1	Merge pull request #2021 from aap-sc/aap-sc/unused_write_warning_fixup fixed warnings about unused parameter when csrs.h file is included	11 months ago
Parshintsev Anatoly	380efd9b80	fixed warnings about unused parameter when csrs.h file is included	11 months ago
Andrew Waterman	70687ccf41	Merge pull request #2015 from binno/fix_mseccfg_write Continue mseccfg write operation even without PMP setting	11 months ago
Andrew Waterman	79907ef8d3	Merge pull request #2014 from binno/fix_vs_exception_delegation Adjust vsdeleg from VSSIP to SSIP interrupt occurred	11 months ago
Andrew Waterman	0f8875631a	Merge pull request #2013 from binno/aia_fix Ensure AIA extension enabled when accessing hvictl	11 months ago
Binno	5d0ab7e1f0	Check H extension enabled when accessing hvictl Signed-off-by: Binno <binno.shen@sifive.com>	11 months ago
Binno	c17d206089	Continue mseccfg write operation even without PMP setting Signed-off-by: Binno <binno.shen@sifive.com>	1 year ago
Binno	46fdf37d65	Adjust vsdeleg from VSSIP to SSIP interrupt occurred Signed-off-by: Binno <binno.shen@sifive.com>	11 months ago
Binno	7c01135f5b	Ensure AIA extension enabled when accessing hvictl Signed-off-by: Binno <binno.shen@sifive.com>	12 months ago

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4067 Commits (c567a199a7dbd9c0f5689e0567415c76d9a21ade) All Branches Search

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