riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Christopher Celio	616cc32c30	Added PC histogram option. - Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag.	12 years ago
Andrew Waterman	2c1ddd1781	Enable runtime loading of dynamic library with --extlib	12 years ago
Andrew Waterman	287a1f87ca	Require libdl for dynamic linking at runtime	12 years ago
Yunsup Lee	0f140bcde4	add hwacha exception support	13 years ago
Yunsup Lee	61d215fc61	commit configure script; new configure option --enable-commitlog	13 years ago
Andrew Waterman	b357c97b24	Remove more vector stuff	13 years ago
Andrew Waterman	de5b42e923	change htif to link against libfesvr	13 years ago
Your Name	e7fb0404b8	Remove dependence on binutils We now have our own disassembler.	15 years ago
Andrew Waterman	77452a26e7	temporary undoing of renaming	15 years ago
Andrew Waterman	740f981cfd	[sim] renamed to riscv-isa-run	15 years ago
Andrew Waterman	481c9e8fd8	[sim] added icache simulator (disabled by default)	15 years ago
Yunsup Lee	4b534147c0	[sim] add disable option for vector	15 years ago
Andrew Waterman	3c6275887f	[sim,pk] reorganized status register	15 years ago
Andrew Waterman	8456c1e923	[pk, sim] added FPU emulation support to proxy kernel	16 years ago
Andrew Waterman	cbefaf68c7	[xcc, sim] changed instruction format so imm12 subs for rs2	16 years ago
Andrew Waterman	01c01cc36f	Reorganized directory structure Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/	16 years ago

16 Commits (c31742961bdab9094c35ef6c1b33186892aa34d1)