riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
307 Commits
53 Branches
3 Tags
19 MiB
Tree: c258e24c0a
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'c258e24c0a'
${ noResults }
Commit Graph

4 Commits (c258e24c0a35632d76b7bebc10ab9c382ccd4823)

Author SHA1 Message Date
Yunsup Lee cb6cfc5f3a refactor disassembler, and add hwacha disassembler
13 years ago
Yunsup Lee 0f140bcde4 add hwacha exception support
13 years ago
Yunsup Lee 2f1f9a4fbc revamp hwacha; now runs in physical mode
13 years ago
Andrew Waterman be9b242d95 Rip out Hwacha for now
13 years ago
Andrew Waterman 30a89f79b3 truncate effective addresses in rv32
13 years ago
Yunsup Lee 2a6e490332 fix utidx assign bug, make ut code execute faster
15 years ago
Yunsup Lee 4f3f70f6b7 fix vf
15 years ago
Andrew Waterman 77452a26e7 temporary undoing of renaming
15 years ago
Andrew Waterman 740f981cfd [sim] renamed to riscv-isa-run
15 years ago
Andrew Waterman e8d6925f0e [sim,opcodes] improved sim build and run performance
15 years ago
Yunsup Lee 68f504c52e [sim] add vector traps to vector instructions
15 years ago
Yunsup Lee e9567ce7bb [sim] add vt stuff
15 years ago
Yunsup Lee fed0e53ae7 [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
15 years ago
Andrew Waterman 3fb2ead615 [xcc,pk,opcodes,sim] updated encoding/insn names
15 years ago
Andrew Waterman 01c01cc36f Reorganized directory structure
16 years ago