riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	2d7af2fb56	Merge pull request #1689 from riscv-software-src/rounding-mode-thread-local Make softfloat's rounding mode thread-local	2 years ago
Andrew Waterman	6c008e990c	Make softfloat's rounding mode thread-local This has no effect on Spike itself, but it might matter for anyone who's using Spike as a library in a multithreaded program.	2 years ago
Andrew Waterman	92d6c3f7f2	Merge branch 'NXP-zilsd'	2 years ago
Christian Herber	70d26d64e6	Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32)	2 years ago
Andrew Waterman	055624200a	Fix a few compile warnings	2 years ago
Andrew Waterman	62d5c06dfb	Merge pull request #1679 from akifejaz/vector-crypto Updated README with supported Vector Cryptography Extensions	2 years ago
Akif Ejaz	22748de594	Merge branch 'master' into vector-crypto	2 years ago
Andrew Waterman	9e6253f8b1	Merge pull request #1687 from riscv-software-src/flw-overlap Separate RV32 and RV64 C instructions into separate files	2 years ago
Andrew Waterman	40b660af4d	Validate contents of overlap list in CI	2 years ago
Andrew Waterman	0325be5559	Separate RV32 and RV64 C instructions into separate files	2 years ago
Andrew Waterman	48f815488e	Improve hit rate of opcode cache to compensate for not mutating insn list	2 years ago
Andrew Waterman	4d23478684	Compensate for perf loss of not mutating insn list by presorting it	2 years ago
Andrew Waterman	625e9451a7	Keep potentially overlapping instructions in order at head of list	2 years ago
Andrew Waterman	acd43e0191	Preserve the ordering of the instruction list	2 years ago
Andrew Waterman	ca38d97e7b	Add comments to overlap list	2 years ago
Andrew Waterman	74ee3b7616	Refine Zicfiss overlap list We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N).	2 years ago
Andrew Waterman	5defb11363	Remove unnecessary instructions from overlap list - c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous	2 years ago
Andrew Waterman	025a50d51a	Add missing instructions to Makefile	2 years ago
Andrew Waterman	9bcda41ef2	Merge pull request #1688 from YenHaoChen/pr-tcontrol triggers: implement tcontrol	2 years ago
YenHaoChen	db762327ef	triggers: implement tcontrol Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0.	2 years ago
Andrew Waterman	00dfa28cd7	Merge pull request #1684 from riscv-software-src/simplify-zicfilp Avoid checking ELP before every instruction fetch	2 years ago
Andrew Waterman	759599553b	Avoid checking ELP before every instruction fetch Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop.	2 years ago
Andrew Waterman	148e6d63e0	No need to check if Zicfilp is enabled before checking ELP ELP will be zero if Zicfilp is not enabled.	2 years ago
Akif Ejaz	dc8ea59215	Merge branch 'master' into vector-crypto	2 years ago
akifejaz	e7d46b8543	corrected the crypto extension version	2 years ago
Jerry Zhao	3a70f84b8a	Merge pull request #1670 from clementleger/dev/cleger/et_dyn add support to load ET_DYN elf	2 years ago
Clément Léger	a316a37331	add support to load ET_DYN elf When compiled as PIE, executable can be loaded at any memory address. Lately, OpenSBI switched to such behavior and spike was not able to load it anymore. This patch add an additional load_offset parameter for load_elf(). This load_offset value is passed as DRAM_BASE and used only for ET_DYN elfs. Signed-off-by: Clément Léger <cleger@rivosinc.com>	2 years ago
akifejaz	6a65a806d2	updated README with supported Vector Cryptography Extensions	2 years ago
Andrew Waterman	a53a71fcc3	Merge pull request #1678 from rbuchner-aril/rbuchner/vxsat-write Require vector extension when attempting vxsat writes	2 years ago
rbuchner	48cf35d027	Require vector extension when attempting vxsat writes Accidentally removed in `c9468f6e02`. See #1660.	2 years ago
Andrew Waterman	5c3cc772b6	Merge pull request #1677 from YenHaoChen/pr-vector-reduction vector: Not logging write of reduction instructions when vl = 0	2 years ago
Andrew Waterman	4611b1f7f9	Merge pull request #1675 from chihminchao/cfi-fix zicflip: fix [ms]ret behavior	2 years ago
YenHaoChen	8ad1b68911	vector: Not logging write of reduction instructions when vl = 0 The spec says: "If vl=0, no operation is performed and the destination register is not updated." in Section 14. Vector Reduction Operations. The commit proposes setting the variable is_write to false when vl = 0, which means not logging the write.	2 years ago
Chih-Min Chao	853105c659	zicflip: fix [ms]ret behavior Based on Spec chapter 3.5 "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively. When executing an xRET instruction, if xPP holds the value y, then ELP is set to the value of xPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED; xPELP is set to NO_LP_EXPECTED." The change follow the last statement after semicolon "xPELP is set to NO_LP_EXPECTED" Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 years ago
Andrew Waterman	2cfd539352	Merge pull request #1257 from YenHaoChen/pr-mcontrol6-hit0-hit1 Implement mcontrol6.hit	2 years ago
YenHaoChen	7657966717	triggers: introduce tinfo.version	2 years ago
YenHaoChen	5e2edf84cc	triggers: implement mcontrol6.hit	3 years ago
YenHaoChen	2855c71b85	triggers: refactor: add typedef enum { ... } hit_t for mcontrol6 Avoid using private headers, e.g., debug_defines.h, in triggers.h	3 years ago
YenHaoChen	2f12bb8c58	triggers: refactor: move mcontrol_common_t::hit to mcontrol_t::hit and mcontrol6_t::hit Add mcontrol_common_t::set_hit()	3 years ago
YenHaoChen	983eb01557	triggers: refactor: update debug_defines.h Update CSR_MCONTROL6_HIT to CSR_MCONTROL6_HIT0 Include CSR_TINFO_VERSION* macros	3 years ago
YenHaoChen	4477cf59f7	triggers: remove mcontrol6.timing (implement suggested trigger timings)	3 years ago
Andrew Waterman	c81d8e73da	Merge pull request #1663 from ved-rivos/zawrs Add Zawrs extension	2 years ago
Ved Shanbhogue	c5229c3f5f	Add Zawrs extension	2 years ago
Andrew Waterman	7438d1e692	Merge pull request #1662 from YenHaoChen/pr-fmaxm_q Zfa: fix: fmaxm.q requires Q instead of D extension	2 years ago
YenHaoChen	6639499526	Zfa: fix: fmaxm.q requires Q instead of D extension	2 years ago
Andrew Waterman	189ca87e1a	Merge pull request #1660 from riscv-software-src/remove-p Remove old P extension	2 years ago
Andrew Waterman	7dd18a0d9c	Update encoding.h	2 years ago
Andrew Waterman	c9468f6e02	Remove Zbpbo, Zpn, and Zpsfoperand implementation	2 years ago
Andrew Waterman	c4edeabbe7	Remove P, Zbpbo, Zpn, and Zpsfoperand from ISA parser	2 years ago
Andrew Waterman	3a4f1702ed	Remove Zbpbo, Zpn, and Zpsfoperand from disassembler	2 years ago

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3548 Commits (c1c0b8b18ca5e5b459c7e506c14e90c02e60a61b) All Branches Search

3548 Commits (c1c0b8b18ca5e5b459c7e506c14e90c02e60a61b)

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