33d80b40d6
Merge pull request #1776 from YenHaoChen/pr-pm
pointer masking: Fix: Let transformed_addr of fetching be unchanged
2 years ago
0648ab40fc
pointer masking: refactor: Use xlen to avoid sketchy, hardcoded number 64
2 years ago
38330930da
pointer masking: Fix: Let transformed_addr of fetching be unchanged
The transformation does not apply to implicit accesses such as instruction fetches.
2 years ago
bfe9173c28
Merge pull request #1769 from riscv-software-src/b-ordering
Fix ordering of B single-letter extension
2 years ago
183a2d0a73
Merge pull request #1770 from YenHaoChen/pr-sim
Fix a typo in f11bd7b
2 years ago
20a508244a
Fix a typo in f11bd7b511
2 years ago
9031c7b651
Fix ordering of B single-letter extension
The canonical order is IMAFDQLCBKJTPVH
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
2 years ago
6f28e4bee5
Merge pull request #1768 from riscv-software-src/commit-log-ordered
Use ordered map for commit log
2 years ago
8b05d84ee9
Use ordered map for commit log
In general, unordered maps should not be used for iteration, only for
lookups.
In this case, using an ordered map guarantees that the order in which
writes are logged is consistent for a given instruction.
Resolves #1499
2 years ago
91793ed7d9
Merge pull request #1764 from ved-rivos/exts
Update readme with recently included extensions
2 years ago
c302e8bd16
Add Smdbltrp
2 years ago
ddba69c980
update readme with extensions
2 years ago
f70b03582f
Merge pull request #1763 from NXP/add-missing-extensions
Add implemented extensions to readme
2 years ago
92833d1270
Add implemented extensions to readme
- Fixes #1761
2 years ago
11fbcb52f4
Merge pull request #1758 from riscv-software-src/csr-init-fixes
Only supply CSRs if corresponding extensions are enabled
2 years ago
1b53bf9364
Merge pull request #1760 from YenHaoChen/pr-mxr
Let MXR not affect implicit memory access for VS-stage address translation
2 years ago
e749bb0923
Let MXR not affect implicit memory access for VS-stage address translation
The behavior of MXR is clarified in https://github.com/riscv/riscv-isa-manual/pull/1543 .
2 years ago
2890ea7212
Merge pull request #1759 from riscv-software-src/dts-api
Improve dts <-> dtb API
2 years ago
1ecad57eae
Only add CSRs if corresponding extensions are enabled
2 years ago
a81d59754f
Remove boilerplate from most CSR instantiations
2 years ago
3c0e6bfa69
Refactor initialization of mode-specific CSRs
The if-statements are boilerplate.
2 years ago
2597b4b4eb
Add CSRs through an interface, rather than mutating csrmap
2 years ago
e98294c3c2
Move CSR initialization to its own file
2 years ago
b9ecc1d4e5
In dtc_compile, use c string instead of stl string
2 years ago
d9f21fc2db
Improve dts <-> dtb API
Avoid exposing the string args to the API.
2 years ago
fdd2570fc4
Merge pull request #1721 from abejgonzalez/dts_parsing
Enable more configuration using the DTB
2 years ago
62a2dd1d26
Merge pull request #1756 from riscv-software-src/clean-up-hpm
Avoid magic constants in hpmcounter implementation
2 years ago
8e05766aa7
Merge pull request #1757 from riscv-software-src/fix-1755
Fix enabling hypervisor extension
2 years ago
39ba3fe46d
Fix enabling hypervisor extension
I introduced a regression in #1753 .
Resolves #1755
2 years ago
eb3ccab33e
Avoid magic constants in hpmcounter implementation
2 years ago
deeda9aa90
Fix trap interactive output
2 years ago
398101b53f
Generalize DTC compilation to support both DTS/B
2 years ago
f11bd7b511
Support parsing procs fully from DTS
2 years ago
6f4116d340
Move isa property to a field of processor_t, not sim_t
This incidentally makes it easier to support heterogeneous-hart configs
in the future
2 years ago
c536affe53
Pass cfg into make_dts
2 years ago
47a57eea73
Merge pull request #1754 from YenHaoChen/pr-vcompress
vcompress.vm: Check if there is any vector extension before using vector CSRs
2 years ago
a17842c0c5
vcompress.vm: Check if there is any vector extension before using vector CSRs
2 years ago
957228319e
Merge pull request #1753 from riscv-software-src/fix-1752
Fix segfault accessing menvcfg when U-mode doesn't exist
2 years ago
584f8551e6
Fix segfault accessing menvcfg when U-mode doesn't exist
The simplest fix is to create the CSRs even if they don't need to exist,
and just skip adding them to the CSR map to prevent the target machine
from being able to access them.
It looks like there are other place we should be following this pattern:
e.g. why does sstatus exist if S-mode does not exist? But that's a
matter for another day.
Resolves #1752
2 years ago
0a2c3b650c
Merge pull request #1750 from YenHaoChen/pr-vector-xrm
vector: Check if there is any vector extension before using vector CSRs
2 years ago
e9f620ffb5
vector: Check if there is any vector extension before using vector CSRs
2 years ago
adacda49e0
Merge pull request #1749 from YenHaoChen/pr-vnclip_wx
vnclip.wx: Check if there is any vector extension before using vector CSRs
2 years ago
54a5e38484
vnclip.wx: Check if there is any vector extension before using vector CSRs
2 years ago
4703ad98bf
Merge pull request #1746 from chihminchao/fix-svpbmt-init
svpbmt: don't reset [mh]envcfg.pbmt to 1
2 years ago
94d21c99f8
svpbmt: don't reset [mh]envcfg.pbmt to 1
The part is introducd by ea70a93
2 years ago
64bc0c1f1d
Merge pull request #1740 from YenHaoChen/pr-fcvtmod_w_d
fcvtmod.w.d: Not update fflags if no exception flag, e.g., exp == frac == 0
2 years ago
e86e653ef3
fcvtmod.w.h: Not update fflags if no exception flag, e.g., exp == frac == 0
2 years ago
1342c687f2
refactor: set_fp_exceptions: Use a new macro raise_fp_exceptions(flags) and refine coding style for clearity
2 years ago
7dce83820e
Merge pull request #1729 from YenHaoChen/pr-require-vector
Fix: Vector CSRs exist without any vector extension since a484f6e
2 years ago
83a2035e40
Merge pull request #1718 from YenHaoChen/pr-pm
Implement pointer masking
2 years ago
Andrew Waterman
YenHaoChen
Jerry Zhao
Ved Shanbhogue
Christian Herber
abejgonzalez
Chih-Min Chao