riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Jerry Zhao	58da6a2232	Merge pull request #1546 from nibrunieAtSi5/patch-2	1 year ago
Nicolas Brunie	fd077496cd	UB in negate in mulh/mulhsu Ensuring No negation on -2^63(int64_t) is performed during mulh/mulhsu Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com> Update riscv/arith.h Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>	2 years ago
Andrew Waterman	49727e8c61	Merge pull request #1889 from ved-rivos/010925 (Guest)Page fault cause by Svnapot occur before A/D update	1 year ago
Ved Shanbhogue	0bbf0d64b4	(Guest)Page fault cause by Svnapot occur before A/D update	1 year ago
Andrew Waterman	fa05e4e4f9	Merge pull request #1887 from fly-1011/fix-hvip-lcofi Fix LCOFI bit implementation in hvip register	1 year ago
room	34195bb81a	Fix LCOFI bit implementation in hvip register	1 year ago
Jerry Zhao	b81b5a0686	Merge pull request #1864 from riscv-software-src/ext_csr_reset Add extension_t csrs in reset(), not register_extension()	1 year ago
Andrew Waterman	4cf4915212	Merge pull request #1881 from riscv-software-src/spike-dasm-strict Add spike-dasm --strict option	1 year ago
Andrew Waterman	8ad998f0e7	Add --strict command-line arg to spike-dasm	1 year ago
Andrew Waterman	1e589aa502	Support strict disassembly in disassembler_t	1 year ago
Andrew Waterman	dc094609b0	Merge pull request #1880 from riscv-software-src/fix-xdebugver Set dcsr.xdebugver to 4, as it ought to be	1 year ago
Andrew Waterman	0fea35ddfb	Set dcsr.xdebugver to 4, as it ought to be See discusson on #1878. This restores the behavior prior to `ec292be4fd`, which inadvertently changed the value to 1. Resolves #1878	1 year ago
Jerry Zhao	a2dcf1fd70	Merge pull request #1871 from XYenChi/patch-1	1 year ago
XYenChi	422c71162f	Fix comment op name Fix op name in the comment Signed-off-by: XYenChi <oriachiuan@gmail.com>	1 year ago
Andrew Waterman	fe49242954	Merge pull request #1870 from riscv-software-src/ci-macos-13 Bump CI version to MacOS 13	1 year ago
Andrew Waterman	df2b69b038	Merge pull request #1866 from chihminchao/prioritize-misaligned-superpage mmu: raise the prioity of misaligned superpage	1 year ago
Andrew Waterman	b2b612631b	Bump CI version to MacOS 13 See https://github.com/actions/runner-images/issues/10721	1 year ago
Chih-Min Chao	6fd2bc9882	mmu: raise the prioity of misaligned superpage Based on the change in ttps://github.com/riscv/riscv-isa-manual/pull/1742 The priority of misaligned superpage is higer that Zicfiss cases Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Jerry Zhao	a10dfd04e7	Add extension_t csrs in reset(), not register_extension() This addresses one issue raised in #1863. register_extension() is only called once, while reset() is called whenever the processor_t is reset. This ensures that extension_t state, including CSRs, is always reset with reset()	1 year ago
Andrew Waterman	7812eabb44	Merge pull request #1862 from NewPaulWalker/fix-hvip Fix WMASK of LCOFI bit(bit 13) in hvip	1 year ago
linzhida	275c668443	Fix WMASK of LCOFI bit(bit 13) in hvip For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of hvip and hvien is implemented and writable.	1 year ago
Andrew Waterman	eb0a3e2b0a	Merge pull request #1860 from XYenChi/master Fix formatting of assembly code within comments	2 years ago
XYenChi	5cc162c482	Fix format	2 years ago
Andrew Waterman	2c67071743	Merge pull request #1859 from ved-rivos/issue_1857 Add missing priv qualification to prev_virt	2 years ago
Ved Shanbhogue	64972b7d9f	Add missing priv qualification to prev_virt	2 years ago
Jerry Zhao	4156e0735a	Merge pull request #1853 from arrv-sc/master feat: add possibility for custom CSRs	2 years ago
Alexander Romanov	adafbd3240	feat: add possibility for custom CSRs Currently in riscv-isa-sim there's no way to make a custom extension that adds new CSRs. This simple patch makes it possible via new virtual function in extension_t class.	2 years ago
Andrew Waterman	fd0a927d5b	Merge pull request #1848 from riscv-software-src/fix-1846 Fix FCSR accesses under Zfinx	2 years ago
Andrew Waterman	1adf60f566	Fix FCSR accesses under Zfinx	2 years ago
Andrew Waterman	ce71e753d3	Remove require_fs macro, as it is only used once	2 years ago
Jerry Zhao	f0d4d42913	Merge pull request #1830 from demin-han/master Fix non-standard interrupt start position	2 years ago
demin.han	2688d179b1	Fix non-standard interrupt start position Signed-off-by: demin.han <demin.han@starfivetech.com>	2 years ago
Andrew Waterman	88fc84ded1	Merge pull request #1839 from ved-rivos/issue_1838 add missing sdt/sie interaction when writing mstatus directly	2 years ago
Ved Shanbhogue	8566627eeb	add missing sdt/sie interaction when writing mstatus directly	2 years ago
Andrew Waterman	fa694e2ae3	Merge pull request #1835 from joe-rivos/fix-ignored-attributes-warning Fix ignored-attributes warning for unique_ptr declaration	2 years ago
Joseph Faulls	a93eb1b808	Fix ignored-attributes warning for unique_ptr declaration The attribute `__nonnull` was added to `fclose` in glibc 2.38, which causes a warning when using its `decltype` on a template argument.	2 years ago
Andrew Waterman	aacfc53770	Merge pull request #1834 from aap-sc/master update encoding.h to get rid of erroneous define	2 years ago
Parshintsev Anatoly	f0a0655a80	update encoding.h to get rid of erroneous define	2 years ago
Andrew Waterman	824ecdf6dc	Merge pull request #1829 from NXP/update-zilsd-to-v0.10 Updated load/store pair for RV32 to v0.10	2 years ago
Christian Herber	ff771919ec	Updated load/store pair for RV32 to v0.10 - renamed Zcmlsd to Zclsd - bumped version number	2 years ago
Andrew Waterman	061a6eaf7b	Merge pull request #1822 from howjmay/typos fix typos	2 years ago
Yang Hau	a41954235b	fix typos	2 years ago
Andrew Waterman	1cf354f9c9	Merge pull request #1823 from YenHaoChen/pr-halt Change -H flag into --halted	2 years ago
Andrew Waterman	382a52638f	Merge pull request #1826 from riscv-software-src/fix-1825 Fix f64_to_bf16 raising underflow when it shouldn't	2 years ago
YenHaoChen	aadd792d6a	Change -H flag into --halted There is a comment about aiming at --halted but failing to achieve so. This commit provides the behavior.	2 years ago
Andrew Waterman	c3f324ff56	Fix f64_to_bf16 raising underflow when it shouldn't Resolves #1825	2 years ago
Andrew Waterman	c95a2cbd68	Merge pull request #1819 from riscv-software-src/ss-cbo-fault Raise store/AMO access fault on CBO to shadow-stack page	2 years ago
Andrew Waterman	00cf1eb2a8	Merge pull request #1820 from YenHaoChen/pr-halt refactor: Remove dcsr::halt variable	2 years ago
YenHaoChen	5c814c7134	refactor: Merge halt and halt_on_reset variables in processor_t	2 years ago
YenHaoChen	871d9453eb	refactor: Move halt out of dcsr Suggested in https://github.com/riscv-software-src/riscv-isa-sim/pull/1816#pullrequestreview-2331806142.	2 years ago

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3548 Commits (c1c0b8b18ca5e5b459c7e506c14e90c02e60a61b) All Branches Search

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