riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	c1c0b8b18c	Merge pull request #1945 from riscv-software-src/fix-jump-table Fix jump-table accesses in MMIO regions	1 year ago
Andrew Waterman	51002ff19f	Fix jump-table accesses in MMIO regions Resolves #1944	1 year ago
Andrew Waterman	fd89a02dbf	Merge pull request #1931 from rogerchang23424/fix-csr Fix CSR initial affected by DTS	1 year ago
Roger Chang	779fc51b7c	Fix CSR initial affected by DTS Add processor_t::reset() method after MMU update by DTS to correct status mask value	1 year ago
Andrew Waterman	f6d41bca17	Merge pull request #1901 from binno/cfi_fixes CFI fixes	1 year ago
Binno	bdac9897a7	Raise store access fault as accessing undefined mmio region by SS instructions * base on CFI spec, ch2.8 The access type is classified as a store/AMO in the event of an access-fault, page-fault, or guest-page fault exception triggered by shadow stack instructions.	1 year ago
Binno	47cc7e844f	Ssrdp should write sign-extension value as xlen is 32	1 year ago
Binno	c1d797abdc	Implement elp state holding mechanism for mnstatus	2 years ago
Binno	060bbd6308	Need zero extend for sspopchk compared vale * when xlen is 32	2 years ago
Andrew Waterman	3c61a0f41e	Merge pull request #1937 from ved-rivos/0317 Shadow stack inst should cause samo access fault	1 year ago
Ved Shanbhogue	f440af14e5	Shadow stack inst should cause samo access fault	1 year ago
Andrew Waterman	947b3949fd	Merge pull request #1934 from NXP/update-zilsd-zmlsd-versions Zilsd and Zclsd moved to ratified version	1 year ago
Christian Herber	51b32b4825	Zilsd and Zclsd moved to ratified version	1 year ago
Andrew Waterman	3f79e3b7de	Merge pull request #1930 from aap-sc/aap-sc/abits_len_fixup increase DTMCS.abits to be compliant debug specification	1 year ago
Parshintsev Anatoly	aa074f2ab0	increase DTMCS.abits to be compliant debug specification ROI from "The RISC-V Debug Specification" (1.0) ``` 3.1. Debug Module Interface (DMI) ... The DMI uses between 7 and 32 address bits. ... ``` NOTE: RISC-V External Debug Specification 0.13.2 has the same sentence.	1 year ago
Jerry Zhao	643e6c6cb0	Merge pull request #1923 from fhunstock-semron/fesvr-non-htif-bootloader-support Fesvr non htif bootloader support	1 year ago
Andrew Waterman	b8eab3090b	Merge pull request #1926 from riscv-software-src/fix-1925 Check for NAPOT PTE validity before raising SS-related faults	1 year ago
Andrew Waterman	283b6af1fa	Check for NAPOT PTE validity before raising SS-related faults Resolves #1925	1 year ago
Friedrich Hunstock	79718ed879	Don't send reset from HTIF, if no binary is given This applies when the binary is set to "none". This is useful when implementing a binary loading mechanism outside of the HTIF, and the bootloader is supposed to boot from that.	1 year ago
Friedrich Hunstock	81d92f3c26	Load symbols even when no binary is given	1 year ago
Tilmann Bartsch	14876b33bc	allow to set tohost/from host via --symbol-elf	2 years ago
Andrew Waterman	9b44f4b997	Merge pull request #1920 from riscv-software-src/zvqdotq Add Zvqdotq extension	1 year ago
Andrew Waterman	5ed426bbf4	Add Zvqdotq extension Not yet frozen, but in a pretty stable state. See https://github.com/riscv/riscv-dot-product	1 year ago
Andrew Waterman	206268cfdf	Merge pull request #1918 from sevan/autotools-infra Autotools infra	1 year ago
Sevan Janiyan	8119565ac1	scripts/install.sh: Delete autoreconf --install now installs "install-sh", drop the old copy.	1 year ago
Sevan Janiyan	3e6e75dded	.gitignore: ignore config.log	1 year ago
Sevan Janiyan	cf06616e02	scripts/config.{guess,sub}: Update autoreconf -i	1 year ago
Sevan Janiyan	7f8c22b337	autoreconf --install	1 year ago
Sevan Janiyan	4df2bd4c5c	riscv/riscv.ac: autoupdate	1 year ago
Andrew Waterman	bbaec510e5	Merge pull request #1915 from chihminchao/fix_undefined_behavior cosim: right shift can't be applied on negative number	1 year ago
Chih-Min Chao	4973c806ef	cosim: fix right shift on neg number and remove redundant mask referece from: ISO C99 (6.5.7/4) "The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated bits are ﬁlled with zeros. If E1 has an unsigned type, the value of the result is E1 × 2E2, reduced modulo one more than the maximum value representable in the result type. If E1 has a signed type and nonnegative value, and E1 × 2E2 is representable in the result type, then that is the resulting value; otherwise, the behavior is undeﬁned." list the affectections. X means it is problematic and fixed by change operand type / redundant mask 1. vsll.v[vxi] -> X X 2. vsra.v[vxi] -> O O 3. vsrl.v[vxi] -> O X 4. vwsll.v[vxi] -> O O 5. vnsrl.w[vxi] -> O O 6. vnsra.w[vxi] -> O X 7. vssrl.v[vxi] -> O X 7. vssra.v[vxi] -> O X Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Sevan Janiyan	a4d2eefb02	configure.ac: autoupdate The preprocessor macro 'STDC_HEADERS' is obsolete.	1 year ago
Sevan Janiyan	36c40295b4	configure.ac: update m4_include paths	1 year ago
Sevan Janiyan	91091dc852	m4/ax_check_compile_flag.m4: Update To latest version from autoconf-archive.	1 year ago
Sevan Janiyan	73de0ffcdb	m4/ax_boost_base.m4: Update To latest version from autoconf-archive.	1 year ago
Sevan Janiyan	efa8eff405	move autoconf-archive extensions to m4/ Follow usual convention, cleans up root directory.	1 year ago
Andrew Waterman	bfb67c1954	Merge pull request #1902 from chihminchao/extend-bf16 Extend bf16	1 year ago
Chih-Min Chao	1b81e407db	softfloat: extend bf16 APIs also add fxx_neg helper functions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Chih-Min Chao	d42570325b	softfloat: change files mode from 755 to 644 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 year ago
Andrew Waterman	cd692c41d6	Merge pull request #1828 from Timmmm/instruction_limit Add instruction limit	1 year ago
Tim Hutt	fdbcde27ce	Add instruction limit Adds an optional --instructions=N CLI argument which will stop the simulation after N instructions. This is useful for benchmarking and profiling and sometimes debugging.	2 years ago
Andrew Waterman	18f4d0ff13	Merge pull request #1904 from YenHaoChen/pr-vcompress vcompress.vm: Check vstart value even if vl = 0	1 year ago
YenHaoChen	3c8562456a	vcompress.vm: Check if there is any vector extension before using vector CSRs	1 year ago
Andrew Waterman	d182829e68	Merge pull request #1907 from kassasAndes/fix-bitmanip-zbs [riscv\|insns] Fix zbs immediate instructions: bclri, bexti, binvi, an…	1 year ago
kassas	2687fa3c48	[riscv\|insns] Fix zbs immediate instructions: bclri, bexti, binvi, and besti for shamt condition	1 year ago
Andrew Waterman	da03b420c2	Merge pull request #1905 from riscv-software-src/fix-pm-misaligned Fix pointer masking for misaligned accesses	1 year ago
Andrew Waterman	aa9918bd54	Fix pointer masking for misaligned accesses Pointer masking needs to be reapplied after computing the address of the tail of a misaligned access in case there's a carry-out into the MSBs. Resolves #1895	1 year ago
Andrew Waterman	10109ae670	Merge pull request #1903 from zqb-all/help-msg-for-dm-no-hasel Fix help message for --dm-no-hasel	1 year ago
YenHaoChen	1434a76e78	Revert "vcompress.vm: Check if there is any vector extension before using vector CSRs" This reverts commit `a17842c0c5`.	1 year ago
Mark Zhuang	2b773d9372	Fix help message for --dm-no-hasel	1 year ago

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