c050d113fe
Support plusarg +h/+help option for HTIF
6 years ago
455b849332
Prevent pmpaddr* and satp from holding invalid physical addresses
Resolves #386
6 years ago
349aba7e5e
Merge pull request #387 from chihminchao/rvv-fix
Rvv fix
6 years ago
3310178000
rvv: fix corner case when input are 1's and shift amount is maximum
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
6e3d1537a4
rvv: remove duplicate vectorUnit declaration
forget to remove the vectorUnit outside, which has been moved
into proccess_t as inner class
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
ff04544e3b
Merge pull request #383 from chihminchao/rvv-commitlog
Rvv commitlog
6 years ago
2596d66552
commitlog: rvv: add commitlog support to misc instrutions
other instructions, which doesn't use macro in decoder.h
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
871b4055d0
commitlog: rvv: add commitlog support to integer instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
9413a45196
commitlog: rvv: add commitlog support to float instrunctions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
e1cb87f7d7
commitlog: rvv: add commitlog support to load instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
4a6b6946bd
commitlog: rvv: change vector register read/write interface
1. add an extra argument to support commitlog
2. move vectorUnit_t into processor_t to avoid circular dependency hell
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
8cf85ffcb3
commitlog: extend reg record to keep multiple accesss
1. use hash to keep duplicated register write since vector has lmul
feature
2. enhance print fuction to support type larger than 64bit
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
7928724c4a
commitlog: extend load/store record to keep multiple access
use vector to store memory accesses
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
816213f776
state: rewrite state_t initialization
implement a specific initalization function to avoid
weird segfault when the member is complex
structure such as map or hash.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
2940a9a604
Make minimum RTI behavior more realistic. ( #375 )
* Make minimum RTI behavior more realistic.
Now DMI will return busy when you'd expect it to, instead of a few scans
later. This only matters when testing OpenOCD. There is no other reason
to use --dmi-rti.
* dmireset only resets busy.
6 years ago
d15d781737
Expose sstatus.vs field
6 years ago
826f05fda0
Merge pull request #378 from chihminchao/rvv-0.8-float64
Rvv 0.8 float64
6 years ago
e75ba052d4
doc: update vector extension version
0.8 is officially released.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
fa2f63818a
rvv: segment load/store needs to check destination range
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
a1ed3764b0
rvv: add vmv[1248]r.v
simple register copy instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
ca648e6e24
rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32
1. fix disam
2. refine checking rule and move them out of loop
3. add missing exception keeping for each element
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
bb1cd8f9e3
Decouple spike-dasm program from simulator code
6 years ago
4ac95a8c99
rvv: refinve vfmv to support float64
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
4436424174
rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 support
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
a94b8914a6
rvv: add vmfxxx.v[vf] float64 support
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
a9dce622c3
rvv: add vfxxx.vf float64 support
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
071d49ac77
rvv: add vfxxx.vv float64 suuport
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b880609510
Merge pull request #366 from chihminchao/rvv-0.8-draft-20191118
Rvv 0.8 draft 20191118
6 years ago
4051af5ce6
rvv: support new mstatus.vs field defined in v0.8
mstatus.vs is similiar to mstatus.fs and used to control the state of
vector unit.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b812e15a8c
rvv: refine fault-first loop
This replaces loop boudary (vlmax) by vl.
In origin, vlmax boundary is used for tail-zero.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b4a5a1b344
rvv: make vlx/vsx match 0.8 spec
1. make offset unsigned
2. refine checking rule
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
c9358be364
rvv: change vmerge/vslideup register checking rule
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
171cfe6bd1
rvv: change vsetvl[i] to match 0.8 spec
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
1c28009cfa
rvv: remove unsupported widen sew
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
3379122ba9
rvv: fix vmadc/vmsbc
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
f7caa6312f
rvv: fix vadc/vsbc
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
c09ec9ce61
rvv: add unsigned average
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
47c0eb64c8
rvv: replace vn suffic by 'w'
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
8d50b2ff66
rvv: fix floating sign inject operand order
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
9b44e1a071
rvv: add load/store whole register instructions
add vl1r.v/vs1r.v
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
fd132e6214
rvv: rename vfncvt suffix and add rod rouding type
1. vfncvt*.v -> vfncvt*.w
2. add vfncvt.rod.f.f.w
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
08343bba3b
rvv: add vqm* 'Quad-Widening Integer Multiply-Add'
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
828c75ca8b
rvv: add quad insn and new vlenb csr
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
d3ac85a9dd
Merge pull request #371 from riscv/fix-vlff
Vector load/store fixes
6 years ago
363c76a894
extend the commit and memory writes log feature with memory reads ( #370 )
6 years ago
0b27475221
Set vstart correctly for vector loads/stores
6 years ago
230d609aeb
Detect too-long segment before starting a vector load
6 years ago
fd89bebdba
Fix first-fault load exception behavior
First-fault loads should only trap on the zeroth element; traps detected
on later elements should just reduce vl.
6 years ago
66cf379234
Simplify vleff.v implementation in the same way as vle.v
6 years ago
33a9196161
Don't terminate first-fault loads on zero data values
6 years ago
James Clarke
Andrew Waterman
Chih-Min Chao
Tim Newsome
John Ingalls