riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Garret Kelly	065ad6b114	htif: catch proper store exception (#44 ) The sim's debug_mmu will generate a trap_load_access_fault if the load fails, not a trap_store_access_fault. This doesn't materially affect exection, but results in a nicer log message.	10 years ago
Andy Wright	8981e57162	Some bugfixes for CSR reading and setting FS for fflags updates (#43 ) * csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0 * Dirty fp state when setting new fp exceptions * Set FS to dirty for all non-zero fflags writes.	10 years ago
Tim Newsome	07d2edff33	Merge pull request #42 from csail-csg/master Removed devicetree.h from riscv.mk.in since it no longer exists	10 years ago
acw1251	2306679f78	Removed devicetree.h from riscv.mk.in since it no longer exists	10 years ago
acw1251	9186ae5876	Added missing header files to riscv.mk.in Merges #40	10 years ago
Andrew Waterman	0d084d5686	Add back IPI support	10 years ago
Andrew Waterman	64fd5f375c	Remove MIPI; mip.MSIP bit is read-only	10 years ago
Andrew Waterman	980a0121e0	Remove tohost/fromhost registers	10 years ago
Andrew Waterman	c3b19169fb	Initialize mtvec to DEFAULT_MTVEC	10 years ago
Andrew Waterman	32e717a3c6	Remove SCRs; add padding after config string	10 years ago
Andrew Waterman	b593e6df7a	Move much closer to new platform-M memory map Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000	10 years ago
Andrew Waterman	9220fdfe95	Add --dump-config-string flag	10 years ago
Andrew Waterman	a9c5b05eca	Remove MTIME[CMP]; add RTC device	10 years ago
Andrew Waterman	27e29e69cc	Split ERET into URET, SRET, HRET, MRET	10 years ago
Andrew Waterman	7a2a57b8bc	Remove non-standard uarch CSRs	10 years ago
Andrew Waterman	10ae74e48a	Allow configuration of default ISA with --with-isa	10 years ago
Andrew Waterman	94c7f5adbe	Update definition of base field in misa register	10 years ago
Andrew Waterman	fa1cb289e7	Fix up interrupt delegation	10 years ago
Andrew Waterman	cb3db40b87	Add counter-enable registers	10 years ago
Andrew Waterman	e6685ad87a	Use RV config string rather than FDT	10 years ago
Andrew Waterman	5618582e2f	WIP on priv spec v1.9	10 years ago
Andrew Waterman	b4bc2159c2	New definitions of misa/marchid/mvendorid	10 years ago
Andrew Waterman	c0c61f09d8	implement PUM functionality	10 years ago
Andrew Waterman	48e4425644	sptbr now a holds a PPN, not an address	10 years ago
Andrew Waterman	82b22f61c7	Return to interactive mode after a trap	10 years ago
Andrew Waterman	8f5523448b	Use simpler MTVEC scheme	10 years ago
Andrew Waterman	8cb6f2ed8b	Fix ERET bug	10 years ago
Andrew Waterman	72b4e74870	Zero-extend all CSR writes This fixes an RV32 HTIF issue.	10 years ago
Andrew Waterman	3cb87f71df	Fix ERET serialization strategy It was screwing up the commit log.	10 years ago
Andrew Waterman	dd1913e777	Add autoconf check for little-endianness	10 years ago
Andrew Waterman	0d5bd9e810	Set default RV32 RAM size to 4 GiB - 256 MiB This allows, by default, 256 MiB of addressable I/O space.	10 years ago
Andrew Waterman	df37931703	Serialize simulator on ERET This guarantees interrupts will eventually be taken.	10 years ago
Andrew Waterman	66a37a5104	WIP on priv spec v1.9	10 years ago
Andrew Waterman	3bfc00ef2a	Compile debug symbols	10 years ago
Andrew Waterman	89ba757daf	Mark SoftFloat routines static inline This avoids duplicate definitions on some platforms.	10 years ago
Andrew Waterman	a95b44df9d	Upgrade to latest SoftFloat	10 years ago
Andrew Waterman	bea283531a	Actually refill ITLB on ITLB miss oops.	10 years ago
Andrew Waterman	853391c2bb	Fix NaN propagation for fcvt	10 years ago
Andrew Waterman	0873901c7c	Remove hwacha support Support for hwacha will continue on the ESP branch (see https://github.com/ucb-bar/esp-isa-sim).	10 years ago
Andrew Waterman	3face89faf	Use new NaN discipline	10 years ago
Andrew Waterman	ca7ea7e820	don't ignore data value when writing MIPI	10 years ago
Andrew Waterman	5344292853	fix help message	10 years ago
Scott Beamer	785762c58a	another osx clang compatability fix	10 years ago
Andrew Waterman	0f622f0e89	C.ADDIW is reserved for rd=0	11 years ago
Andrew Waterman	0c3af3d73a	Generate device tree for target machine	11 years ago
Andrew Waterman	a7bde15c2b	Access FP regs through a macro This makes it easier to hook into them.	11 years ago
Andrew Waterman	0e3fde1bb5	Merge pull request #34 from zizztux/incorrect_int_reg_count Fix incorrect upper limit for loop on interactive int register display.	11 years ago
SeungRyeol Lee	fe513f83ca	Fix incorrect upper limit for loop on interactive int register display.	11 years ago
Andrew Waterman	2ace4c98e6	Fix histogram for RVC No need to right-shift PC by 2. It's a map, so this is a false economy.	11 years ago
Andrew Waterman	575054bc4e	Update to hopefully final RVC 1.9 encoding	11 years ago

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