bf8d2b71bb
AMOs should always return store faults, not load faults
This commit also factors out the common AMO code into mmu_t.
10 years ago
ecff67fb34
Make reading/writing fpu regs work.
Temporarily turn them on in mstatus if necessary.
10 years ago
53db924b02
Minor code cleanup.
10 years ago
0b554a92ff
Check for exception after register write.
10 years ago
2c5e725666
Check for exception after reading a register.
10 years ago
210d50a01f
Fix error message.
It was erroneously complaining that gdb sent too much data even when it
wasn't.
10 years ago
53d74f4cc3
Increase gdb receive buffer.
Newer gdbs send larger memory write packets when downloading.
Also improve error reporting when gdb sends packets that don't fit in
the buffer.
10 years ago
db6051f200
Don't force load trigger timing to After
Allow the CSR writer to make the choice.
@timsifive @colinschmidt this fixes the failing rv64mi-p-breakpoint test.
10 years ago
438a337fa0
Don't die when gdb thinks XLEN is 64 but it's 32.
Instead, just give gdb what it asks for.
Also when gdb does a register write, let the user know that it's likely
misconfigured and tell them how to fix it.
This is probably as well as issue #72 can be fixed in spike.
10 years ago
8b3ef13471
Return an error to gdb when memory reads fail. ( #71 )
10 years ago
02027ca74c
Update trigger behavior. ( #70 )
M-mode writes to tdata1 with dmode set are ignored instead of raising an
exception.
Add the same behavior for tdata2.
10 years ago
5762bedab3
restore clang support by fixing printf identifiers
10 years ago
167a876c4f
allow MAFDC bits in MISA to be modified
10 years ago
de9ebf704e
Remove generic debug tests. ( #65 )
They live in riscv-tests/debug now, since they also test gdb, and can be
used to test other targets besides spike.
10 years ago
3032e25ae6
Merge pull request #62 from riscv/trigger
Implement address and data triggers.
10 years ago
d49dd8b60e
Merge branch 'master' into trigger
Conflicts:
riscv/encoding.h
riscv/processor.cc
10 years ago
10d1bff0a1
Rebuild debug ROM because CSR encoding changed.
10 years ago
2b390a9dea
Support triggers on TLB misses.
10 years ago
e464ab8efb
Theoretically support trigger timing.
10 years ago
84f5c416bf
Rename tdata[0-2] to tdata[1-3].
Add timing bit (but it doesn't do anything).
Implement dmode bit.
10 years ago
0bd33edd80
Save/restore tselect. Set dmode.
10 years ago
6be7552735
Fix indent.
10 years ago
1a01326bf9
Rename tdata0--tdata2 to tdata1--tdata3.
10 years ago
e15a1f99fd
Add (degenerate) performance counter facility
10 years ago
11ef82c726
Allow reads from tdrdata registers
10 years ago
bc49f60710
partially update spike to newer debug spec
10 years ago
c8149cb261
Fix spike interactive (-d) mode
10 years ago
b3e6c1d929
remove HWBPCOUNT field of DCSR
10 years ago
d6dae45182
Implement address and data triggers.
So far I only have testcases for instruction and data address.
Not implemented is the mechanism that lets the debugger prevent a user
program from using triggers at all. I'll be adding that soonish.
The critical path is unchanged, but my experimenting shows the
simulation is slowed down about 8% by this code. Reducing the size of
trigger_match() (which is never called during my benchmark) fixes that,
but making it not be inlined has no effect. I suspect the slowdown comes
from cache alignment or something similar, and on a different CPU or
after more code changes the speed will come back.
10 years ago
5e1d005935
Allow mstatus.MPP to store bad values; instead, validate on MRET
Either approach is legal, but this more closely matches Rocket.
10 years ago
eb19d1c1de
remove old rvc directory ( #61 )
10 years ago
4fcc71ee8a
Add support for virtual priv register. ( #59 )
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
10 years ago
5daafcde73
Set U bit in misa register
10 years ago
8a0e5d2ed3
Make address translation work in 32-bit. ( #58 )
10 years ago
75494f3abd
Fix single step over csrw instructions. ( #57 )
csrw instructions instantly return if the PC isn't serialized. Take note
of this, and don't enter debug mode until the instruction we just
executed actually completed.
10 years ago
da0bc312ae
Don't treat RVC NOP as illegal instruction
10 years ago
1b797b1aac
Fix page table walker not respecting valid bit
10 years ago
e10d2def7d
Update to new PTE format
10 years ago
6f64a1f72e
Remove debug printf that was cluttering up output.
10 years ago
03b8bad375
Disassemble RVC instructions based on XLEN
The interpretation of RVC opcodes depends on XLEN, and the disassembler
always assumed RV32.
h/t Michael Clark
10 years ago
9b960e91b4
Make gdbserver code work with small Debug RAM.
10 years ago
d723c6772d
Support debugging 32-bit spike instances.
10 years ago
8861244f8d
Parameterize debug ROM contents on XLEN
10 years ago
965571945c
Remove fence.i from debug ROM
10 years ago
7b9cd3e781
Don't use I$ in debug mode
This avoids the need for fence.i.
10 years ago
036c908666
Remove legacy HTIF; implement HTIF directly
10 years ago
b7fb80ccf5
Fix paddr_bits computation prior to VM setup
10 years ago
03d4f02158
Merge sasid into sptbr
10 years ago
f5ecf65e5e
Trap on tdrdata registers when tdrselect[XLEN-1]=0
10 years ago
ab2858e065
make check: Fail if the tests failed
10 years ago
Andrew Waterman
Tim Newsome
Andrew Waterman
Scott Beamer
Andrew Waterman
Colin Schmidt
Jonathan Neuschäfer