Andrew Waterman
|
be3414250d
|
Add test program for dummy rocc
Should move this elsewhere
|
13 years ago |
|
Andrew Waterman
|
bbb0f2179c
|
Implement RoCC and add a dummy RoCC
Enable it with --extension=dummy
|
13 years ago |
|
Andrew Waterman
|
04c2d491c4
|
Instructions are no longer member functions
|
13 years ago |
|
Andrew Waterman
|
b0af18ed44
|
Ignore JALR's effective address LSB
|
13 years ago |
|
Andrew Waterman
|
15daa31a54
|
Disentangle some header files
|
13 years ago |
|
Andrew Waterman
|
d36c661765
|
Rename MTFSR/MFFSR to FSSR/FRSR
|
13 years ago |
|
Andrew Waterman
|
d9bef8871f
|
Swap J and JALR encoding
|
13 years ago |
Quan Nguyen
|
a39658bf83
|
Fix eret (again)
* Set SR_S if SR_PS is set, not the other way around
(that is, set SR_S if SR_PS is not set).
|
13 years ago |
|
Andrew Waterman
|
7a05cbde17
|
Fix dumb ERET bug
|
13 years ago |
|
Andrew Waterman
|
d148b8aac3
|
Don't flush TLB on PTBR writes (only FATC)
|
13 years ago |
|
Andrew Waterman
|
7a16302b4d
|
New supervisor mode
|
13 years ago |
|
Andrew Waterman
|
b357c97b24
|
Remove more vector stuff
|
13 years ago |
|
Andrew Waterman
|
bda232b011
|
Rename MFTX/MXTF to FMV
|
13 years ago |
|
Andrew Waterman
|
be9b242d95
|
Rip out Hwacha for now
|
13 years ago |
|
Andrew Waterman
|
5a97139eee
|
Rip out RVC for now
|
13 years ago |
|
Andrew Waterman
|
0de1489e8a
|
Generate instruction decoder dynamically
This will make it easier for accelerators to add instructions.
|
13 years ago |
|
Andrew Waterman
|
d237ebbd5c
|
Remove JALR static hints
|
13 years ago |
|
Andrew Waterman
|
2c87b07a1d
|
Kill spike when xspike is SIGINTed
|
13 years ago |
|
Andrew Waterman
|
9291e2deed
|
Don't use stdout for debugging
|
13 years ago |
|
Andrew Waterman
|
a68c33c2a4
|
Add xspike program
|
13 years ago |
|
Andrew Waterman
|
97a9245bdd
|
Use calloc to allocate target memory
It just calls mmap under the hood, anyway...
|
13 years ago |
|
Andrew Waterman
|
9299f2f745
|
Eliminate infinite loop in debug mode
|
13 years ago |
|
Andrew Waterman
|
790db6c910
|
Exit cleanly from debug console
|
13 years ago |
|
Andrew Waterman
|
b6da69bb3e
|
Favor procs.size() over num_cores()
|
13 years ago |
|
Andrew Waterman
|
6de0c1e324
|
Fix SR_U64 bit being ignored
|
13 years ago |
Andrew Waterman
|
34be1b9afd
|
make spike.o correctly depend on dispatch.h
|
13 years ago |
|
Andrew Waterman
|
3148ee1df5
|
use coreutils `seq' instead of hacky `range'
|
13 years ago |
Yunsup Lee
|
a9d1c3de84
|
change riscv-isa-run to spike in documentation
|
13 years ago |
|
Yunsup Lee
|
28b983b266
|
fix make issue
|
13 years ago |
|
Yunsup Lee
|
b3f7c6045c
|
change riscv-isa-run to spike
|
13 years ago |
|
Andrew Waterman
|
9c0fe41baa
|
make Makefile sh-friendly
|
13 years ago |
|
Andrew Waterman
|
b363c55cfe
|
use inttypes macros to print uint64_t
|
13 years ago |
|
Andrew Waterman
|
14cfc50a60
|
fix(?) circular dependence on generated headers
|
13 years ago |
|
Andrew Waterman
|
adb3e3df44
|
add range(start, end) method to Makefile
|
13 years ago |
|
Yunsup Lee
|
4944ab3c02
|
fixes to correctly simulate the vector unit
|
13 years ago |
|
Andrew Waterman
|
789abb77fb
|
make interactive mode cope with canonical terminal
|
13 years ago |
|
Andrew Waterman
|
60a69f08bf
|
destroy htif on simulator termination
|
13 years ago |
|
Andrew Waterman
|
c43f02f294
|
correctly depend on dispatch.h
|
13 years ago |
|
Andrew Waterman
|
6c19a775f9
|
remove circular dependence in Makefile
Thanks, Sebastien!
|
13 years ago |
|
Andrew Waterman
|
24cf9ccbb5
|
update abi register names
|
13 years ago |
|
Andrew Waterman
|
8ec519af68
|
add AUIPC insn; remove RDNPC insn
|
13 years ago |
|
Andrew Waterman
|
b189b9b128
|
add load-reserved/store-conditional instructions
|
13 years ago |
|
Andrew Waterman
|
983a062e28
|
ignore writes to SR IP field
|
13 years ago |
|
Andrew Waterman
|
93229b56ba
|
opcodes.h must only contain DECLARE_INSN() lines
|
13 years ago |
|
Andrew Waterman
|
28ac3dbd81
|
add BSD license
|
13 years ago |
|
Andrew Waterman
|
41ba91339e
|
update ancient README
|
13 years ago |
|
Andrew Waterman
|
30a89f79b3
|
truncate effective addresses in rv32
also, employ a more efficient instruction dispatch based upon rv32 mode.
|
13 years ago |
|
Andrew Waterman
|
aaf96970cc
|
expose pending interrupts in status register
|
13 years ago |
|
Andrew Waterman
|
7abd96d407
|
add missing #include
|
13 years ago |
|
Andrew Waterman
|
c0f8506da0
|
ignore host writes to fromhost if old value not 0
|
13 years ago |
