riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Tim Newsome	bd17c7e5a8	Add -H to start halted.	11 years ago
Tim Newsome	d1ba8b5593	gdb can now read spike memory. The endianness is wrong, but I think it might be that gdb doesn't have it right. Need to investigate what architecture gdb thinks it's debugging.	11 years ago
Tim Newsome	9f1ea45e41	Listen on a socket for gdb to connect to. So far it just listens, and gdb times out because it's not getting any messages back. Receive packets and verify their checksum.	11 years ago
Andrew Waterman	b593e6df7a	Move much closer to new platform-M memory map Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000	10 years ago
Andrew Waterman	9220fdfe95	Add --dump-config-string flag	10 years ago
Andrew Waterman	10ae74e48a	Allow configuration of default ISA with --with-isa	11 years ago
Andrew Waterman	5344292853	fix help message	11 years ago
Prashanth Mundkur	b16ef94394	Add an option (-l) to display a log of execution in non-interactive mode. Interactive (-d) mode overrides this option when both are specified.	11 years ago
Andrew Waterman	c4350ef6ef	Support setting ISA/subsets with --isa flag Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha	12 years ago
Andrew Waterman	416c8be88c	Support building from within root directory	12 years ago
Andrew Waterman	590417bec9	Factor out the dummy RoCC accelerator	12 years ago
Christopher Celio	616cc32c30	Added PC histogram option. - Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag.	12 years ago
Andrew Waterman	2c1ddd1781	Enable runtime loading of dynamic library with --extlib	13 years ago
Andrew Waterman	fb3be24671	Eliminate hwacha <-> riscv circular dependence We now split out the spike executable into another subproject, which depends on both rocket and hwacha	13 years ago
Andrew Waterman	d5204838b7	Pass target machine's return code back to OS	13 years ago
Yunsup Lee	2f1f9a4fbc	revamp hwacha; now runs in physical mode	13 years ago
Andrew Waterman	bbb0f2179c	Implement RoCC and add a dummy RoCC Enable it with --extension=dummy	13 years ago
Andrew Waterman	a68c33c2a4	Add xspike program	13 years ago
Andrew Waterman	790db6c910	Exit cleanly from debug console	13 years ago
Yunsup Lee	a9d1c3de84	change riscv-isa-run to spike in documentation	13 years ago
Yunsup Lee	b3f7c6045c	change riscv-isa-run to spike	13 years ago
Andrew Waterman	28ac3dbd81	add BSD license	14 years ago
Andrew Waterman	290c702c0f	specialize fully-associative caches the dumb linear search of a set's tag array was far too slow	14 years ago
Andrew Waterman	b119073ab0	add I$/D$/L2$ simulators	14 years ago
Andrew Waterman	de5b42e923	change htif to link against libfesvr	14 years ago
Andrew Waterman	6405097bf2	remove debug printf	15 years ago
Andrew Waterman	23688da201	poll HTIF occasionally	15 years ago
Rimas Avizienis	91edaf151d	added #include <stdlib.h> to get rid of errors building with gcc-4.4 on ubuntu	15 years ago
Andrew Waterman	77452a26e7	temporary undoing of renaming	15 years ago
Andrew Waterman	740f981cfd	[sim] renamed to riscv-isa-run	15 years ago
Andrew Waterman	d6fd350f0c	[xcc] cleaned up mmu code	15 years ago
Andrew Waterman	46f2fb1d9e	[sim] hacked in a dcache simulator	16 years ago
Andrew Waterman	481c9e8fd8	[sim] added icache simulator (disabled by default)	16 years ago
Yunsup Lee	133806b398	[sim] various fixes to get the sim work with the fesvr	16 years ago
Andrew Waterman	d2c5b5c159	[pk,sim] first cut of appserver communication link	16 years ago
Andrew Waterman	01c01cc36f	Reorganized directory structure Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/	16 years ago

10 Commits (bd17c7e5a80c21b8b7dd6be8cd24a6f89dd63bf0)