* add DECLARE_OVERLAP_INSN to bind instructions with extension
* add overlap_list.h to contain the declare of all overlapping instructions
* make func function for overlapping instruction return NULL when the coresponding
extension(s) is not supported.
This includes skipping store in store_slow_path.
Is okay to skip the mmio_store part too, since the access_fault for mmio_failure will be caught on the actual store.
The ordering for the mmio_access fault is irrelevant since it will occur after the TW faults, and load faults are converted to store faults.
Will catch any faults from the access but won't perform a store.
Since store permissions can only be granted if read permissions exist,
any store faults will occur before or at the same time as a load fault.
Thus this store permissions check is sufficient for properly catching the faults in an Amo access TW.
The only slightly difficult thing here is that hartids will always
be considered "overridden" by the time we get to sim_t::sim_t (either
overridden by a command line argument, or overridden when we set
default hartids just before the constructor). To allow downstream code
to distinguish between "I picked IDs 0, 1, 2, 3 because the user asked
for 4 processors" and "The user explicitly asked for IDs 0, 1, 2, 3",
we have an extra explicit_hartids field.
We now parse to a std::vector<int> and then set the "hartids" variable
to the result.
There is a slight functional change here, in that if you pass
"--hartids 1,2,3 --hartids 4,5", you'll now get 2 cores with ids of
4,5 rather than 5 cores with ids of 1,2,3,4,5. This is what most tools
do with repeated command line arguments and I suspect the old
behaviour was actually by accident!
The motivation here is mostly to enable a refactoring where the memory
layout (sans allocated memory) gets passed to DTS/DTB code before we
ever allocate anything.
But it turns out to make merge_overlapping_memory_regions a bit
simpler, which is an added bonus.
The write mask is incorrectly computed by hgatp_csr_t::unlogged_write()
which leads to hgatp.PPN bits not getting updated upon hgatp CSR write.
This patch fixes hgatp CSR writes and gets KVM RISC-V working again
on Spike.
Fixes: 70b7e9ca2d ("mmu: support asid/vmid (#928)")
Signed-off-by: Anup Patel <anup@brainfault.org>
The alternative would be to #undef set_csr after including encoding.h,
but this solution strikes me as cleaner. Part of the reason is that
set_csr was not a great name: it sounds like it implements the CSRRS
(read & set) instruction, rather than impelementing a simple write.
The change makes [v]satp.asid and hgatp.vmid writtable and supports
maximum length for rv32 and rv64. Software could write and read the
satp.asid to get the valid length or check if the core supports
asid/vmid or not. However, there is no official way to describe this hardware
capability (device tree or something else). Two implementation flags
are also added for future use and enabled by default.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Andrew Waterman
Weiwei Li
Ryan Buchner
Rupert Swarbrick
Rupert Swarbrick
Scott Johnson
Anup Patel
Brandon Wu
4vtomat
Tim Newsome
Chih-Min Chao
Mark Fedorov