riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
joey0320	b98e922cb4	Fix Spike --device option to pass on args to downstream plugins	3 years ago
YenHaoChen	e9ae2287e1	typo: vwsll.vi: fix a typo on disassembling vwsll.vi Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>	3 years ago
Andrew Waterman	0c1397661c	Merge pull request #1516 from YenHaoChen/pr-dcsr-ebreakx fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege modes	3 years ago
YenHaoChen	a62b69a889	fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege modes	3 years ago
Andrew Waterman	3bc4f0f8fd	Merge pull request #1514 from f0rget-the-sad/multi-rb remote_bitbang: make send_buf class member	3 years ago
Volodymyr Fialko	a68f2caafb	remote_bitbang: make send_buf class member Currently send buffer is static variable in function, which makes it's impossible to have multiple concurrent instances of remote bitbang class, since all of them would share this static buffer. Thus, make send_buf a class member. Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>	3 years ago
Andrew Waterman	90aa49f85b	Merge pull request #1511 from YenHaoChen/pr-stimecmp stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in HS-mode	3 years ago
YenHaoChen	6e6885feed	stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in HS-mode The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a mode other than M-mode. The previous implementation does not check the permission on accessing vstimecmp in HS-mode. This commit fixes the issue by moveing the permission check from virtualized_stimecmp_csr_t to stimecmp_csr_t, which implements the vstimecmp.	3 years ago
Andrew Waterman	4841ad0238	Fix FMVP.D.X implementation Resolves #1507	3 years ago
Tim Newsome	be5dee0baf	Merge pull request #1500 from riscv-software-src/debug_tests Update debug smoketest action.	3 years ago
Tim Newsome	ca84e5325e	Update debug smoketest action. To get https://github.com/riscv-software-src/riscv-tests/pull/522, which fixes an intermittent failure.	3 years ago
Andrew Waterman	4f916978cd	Merge pull request #1498 from f0rget-the-sad/htif-stop-on-signal fesvr/htif: allow exit on SIGINT.	3 years ago
Volodymyr Fialko	f04be98493	fesvr/htif: allow exit on SIGINT. Currently signal handler would call exit() only on second received signal, this prevent proper program cleanup. Instead use signal flag to exit loop. Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>	3 years ago
Andrew Waterman	5f576bd5c2	Merge pull request #1490 from iamKarthikBK/master Add support for setting PMP Granularity over CLI	3 years ago
Karthik B K	5bdb9d4d7e	expose pmp granularity as a cli option. PMP Granularity is made available as a command line option. The default value is 4 Bytes. The value can be changed by passing the option --pmp-granularity=<value> to spike. Signed-off-by: Karthik B K <karthik.bk@incoresemi.com>	3 years ago
Andrew Waterman	5a1145742e	Merge pull request #1491 from ved-rivos/zabha Add unratified Zabha extension	3 years ago
Ved Shanbhogue	5a98459156	Add Zabha instructions to make	3 years ago
Ved Shanbhogue	04cbaf0c1c	Add Zabha instructions to disasm	3 years ago
Ved Shanbhogue	2adfab25a5	Add enum for Zabha extension	3 years ago
Ved Shanbhogue	b96bf55654	Add encodings for Zabha instructions	3 years ago
Ved Shanbhogue	8dda7a208d	add halfword width amo instructions	3 years ago
Ved Shanbhogue	08bad17b04	add byte width amo instructions	3 years ago
Andrew Waterman	eeef09ebb8	Merge pull request #1489 from nibrunieAtSi5/patch-1 Fixing minor typo in comment Gallois -> Galois	3 years ago
Nicolas Brunie	434138e109	Fixing minor typo Gallois -> Galois Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>	3 years ago
Andrew Waterman	f6104dd6ca	Merge pull request #1487 from mehnadnerd/zalasr Adding Zalasr support.	3 years ago
brs	37e00ffb6e	Update README on adding new instructions to point out that they need to be added to riscv.mk.in	3 years ago
brs	177ecae365	Update to Zalasr encodings to require the aq/rl bits be set rather than assuming they are	3 years ago
brs	9258b59e67	Spike support for the Zalasr extension	3 years ago
Andrew Waterman	67252b3d7c	Merge pull request #1486 from riscv-software-src/zcmop Add unratified Zcmop extension	3 years ago
Ved Shanbhogue	762ed3f5c8	add zcmop extension instructions	3 years ago
Andrew Waterman	4eb1cceb3d	Revert "tmp" This reverts commit `1de1e81952`.	3 years ago
Andrew Waterman	a2e80e1eba	Merge pull request #1484 from riscv-software-src/zcmop add zcmop extension instructions	3 years ago
Andrew Waterman	1de1e81952	tmp	3 years ago
Andrew Waterman	36b21070c5	Merge pull request #1483 from riscv-software-src/debug_tests workflow: Update riscv-openocd and riscv-tests versions	3 years ago
Tim Newsome	68d4f6faff	workflow: Update riscv-openocd and riscv-tests versions Make sure we test with recent OpenOCD and tests.	3 years ago
Andrew Waterman	6986742686	Merge pull request #1481 from chihminchao/remove-vector-amo Remove vector amo	3 years ago
Chih-Min Chao	e84ef9385c	vamo: remove disassembler Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Chih-Min Chao	9ffcbc3556	vamo: remove related loop macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Chih-Min Chao	9705dc3ba8	vamo: remove instruction implementation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Chih-Min Chao	2e24763045	vamo: remove from building list Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Andrew Waterman	b5d13f3605	Merge pull request #1477 from abejgonzalez/patch-1 Update dtm.h with switch_to_* functions	3 years ago
Abraham Gonzalez	c5eee7426d	Update dtm.h with switch_to_* functions Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>	3 years ago
Andrew Waterman	d1efcdffff	Merge pull request #1473 from riscv-software-src/unavailable Fix behavior of unavailable harts.	3 years ago
Tim Newsome	77e9aaef19	debug: Abstract commands fail on unavailable harts.	3 years ago
Tim Newsome	7613da4d26	debug: Halted harts can also be unavailable.	3 years ago
Andrew Waterman	847fe5d59a	Merge pull request #1471 from mehnadnerd/patch-1 Change disasm for vset{i}vli with reserved vtypes to display the reserved bits	3 years ago
Brendan Sweeney	cf3f787474	Change disasm for vset{i}vli with reserved vtypes to display the reserved bits Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly. This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler. GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired. Signed-off-by: Brendan Sweeney <brs@eecs.berkeley.edu>	3 years ago
Andrew Waterman	67df25aedc	Merge pull request #1458 from YenHaoChen/pr-multiple-icount Hit multiple icount triggers with different actions	3 years ago
YenHaoChen	9bc80f3d09	triggers: fix: not decrease icount.count on firing other icount with action=debug	3 years ago
YenHaoChen	7b3b2e94ad	triggers: refactor: icount: breakdown detect_icount_match() into detect_icount_fire() and detect_icount_decrement()	3 years ago

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3065 Commits (b98e922cb42d4e7ebe7e76ce413acc8594294068) All Branches Search

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