b3855682c2
Add missing stdexcept imports
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
6 years ago
b1de71f464
Merge pull request #458 from chihminchao/rvv-fp16
Rvv fp16
6 years ago
cc1e7164bf
parser: fp16: require F extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
073c84163a
rvv: fp16: support element movement instructions
vfmv/vfslide/vfmerge
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
5ba5c15188
rvv: fp16: support vfwxxx.[wv][vf] instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
d09689d271
rvv: fp16: support conversion instrucitons
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
aa05cc8747
rvv: fp16: support reduction instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
dac8944fa2
rvv: fp16: support comparison instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
aaf76d8430
rvv: fp16: support .vf instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b216e03dd1
rvv: fp16: support .vv instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
d78999f0c7
rvv: remove unused WIDE_END loop macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
817fb0799f
fp16: add helper macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
2b38341691
sf: fp16: add missing APIs
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b6432b1edf
Merge pull request #452 from davetw/mem_region_check
Check and handle the memory regions when user specified memory regions
6 years ago
a3835d41cc
Merge pull request #457 from chihminchao/partial-log
rvv: commitlog: report status when memory trap occurs in vector load/…
6 years ago
7ce1d973c9
rvv: commitlog: report status when memory trap occurs in vector load/store
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
7851d2c525
Merge pull request #456 from chihminchao/rvv-fix-2020-04-28
rvv: commitlog: fix vmsgtu.vi and vmsleu.vi dst information
6 years ago
020e9aa441
rvv: commitlog: fix vmsgtu.vi and vmsleu.vi dst information
Comparison only writes one vector register
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
11726bc1b4
Fix vnclip.wi bug
Rounding needs extra intermediate precision.
Looks like the fix was already made to vnclip.wx and vnclip.wv,
but wasn't made here.
cc @chihminchao
6 years ago
63feddee1d
merge the overlapping or containing memory regions when user specified
the memory regions (-m)
6 years ago
9a919d0866
Merge pull request #448 from chihminchao/rvv-spec-0.9
Rvv spec 0.9
6 years ago
f357236eb5
rvv: udpate readme for spec version
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
fdd146a802
parser: exhance --isa to support extended extension
1. support extended extension
ex:
--isa="imadc_zfh
2. relax extension character order
--isa=imadc or --isa==cdima
3. use another bit structure to keep all supported extensions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
8889d21389
rvv: commitlog: fix dst information for int comparison
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
fd8a6369fa
rvv: disasm: leave only SEW-bit segment load/store
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
f5be48f027
rvv: leave only SEW-bit segment store
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
81686eae2e
rvv: leave only SEW-bit segment load
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
7b3d88f5de
rvv: add vfslide1[down|up].vf and refine checking rule
1. new features in spec 0.9
2. also fix destination commitlog information for integer comparison
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
a261be3dc6
rvv: add float conversion for rtz variants
new features in spec 0.9
ref:
https://github.com/riscv/riscv-v-spec/issues/352
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
2dd63195c0
rvv: fix vcsr related status change
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
d1b6eb1113
Move vxrm/vxsat from fcsr to vcsr
See 951b64fb10
6 years ago
ecb15182b5
Handle misaligned memories by aligning them, rather than erroring
Resolves #442
6 years ago
220ae7ec6b
Merge pull request #443 from chihminchao/rvv-fix-2020-04-09
Rvv fix 2020 04 09
6 years ago
26fc332c38
rvv: minor optimization for index load loop
skip when vl == 0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
1077d07572
rvv: vslide[1]up now allows mask overlap when LMUL=1
See https://github.com/riscv/riscv-v-spec/pull/407
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
38b2a00e6c
rvv: fix index segment load overlapping check
dst group can't overlap src group for segment case
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b6f7b65b65
op: update CSR
1. add new hypervisor csr
2. add debug module csr
3. add some new high part register for rv32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
942662a233
rvv: missing vector enabling check for mask operation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
c069be72bb
option: flag x extension without loading shared lib ( #439 )
reserve the word 'dummy' to set the x-extension in misa but not to load
a related shared library.
ex:
--isa=IMACXdummy
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
5d5ee23f57
Deny hart access to debug CSRs when not in D-mode
Follow-on to 1ef875316a@timsifive
6 years ago
858ffef27f
Assert that debug_module is initialized correctly. ( #437 )
This would have prevented the regression in #409 .
6 years ago
5c315d3c3f
Merge pull request #436 from riscv/fix-435
When enabling the debug module, poll til it's really enabled
6 years ago
acd953afd2
When enabling the debug module, poll til it's really enabled
Resolves #435
6 years ago
a346ad57a2
Fix debug segfault by partially reverting #409
6 years ago
1ff8764fa0
Merge pull request #433 from chihminchao/rvv-fix-2020-03-27
Rvv fix 2020 03 27
6 years ago
bf296ca064
Write execution logs to a named log file ( #409 )
This patch adds a --log argument to spike. If not given, the behaviour
is unchanged: messages logging execution of instructions and (if
commit logging is enabled) commits go to stderr.
If --log=P is given, Spike now writes these messages to a log file at
the path P. This is nice, because they are no longer tangled up with
other errors and warnings.
The code is mostly plumbing: passing a FILE* object through to the
functions that were using stderr. I've written a simple "log_file_t"
class, which opens a log file if necessary and yields it or stderr.
6 years ago
7760d6d68b
rvv: fix int_max/min value calculation
1. use stdint macro
2. fix vxsat status for vsmul
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
425e39b009
rvv: fix vssra.vi e64 corner case
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
8977224a42
rvv: check vlen == slen
For current implementation, vlen must be equal to slen. It will be added
in the future.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
a91e62f6c1
rvv: fix vmv reg checking failure
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
Schuyler Eldridge
Andrew Waterman
Chih-Min Chao
Han-Kuan Chen
Dave.Wen
Chih-Min Chao
Tim Newsome
Rupert Swarbrick