riscv-isa-sim

3 Tags

19 MiB

Tree: b1dc3826d0

Author	SHA1	Message	Date
Chih-Min Chao	6cb10a7fc4	fdt: import fdt library from OpenSBI Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	77adcb1ec9	rvv: add simple instruction parsing tool the tool can parse the instruction name from spike debug log to help dsp kernel designer check what instructions have been used Signed-off-by: Jerry Shih <bignose1007@gmail.com>	7 years ago
Andrew Waterman	f49618ca9d	Add fesvr; only globally install fesvr headers/libs	7 years ago
Andrew Waterman	c4350ef6ef	Support setting ISA/subsets with --isa flag Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha	11 years ago
Andrew Waterman	17fd25f267	Rename riscv-dis to spike-dasm This is a better name, since it looks for the string DASM(xxx), and it fixes tab completion for the cross compiler.	12 years ago
Andrew Waterman	416c8be88c	Support building from within root directory	12 years ago
Andrew Waterman	b06c8e9f26	Implement timer faithfully rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed.	12 years ago
Andrew Waterman	590417bec9	Factor out the dummy RoCC accelerator	12 years ago
Andrew Waterman	fb3be24671	Eliminate hwacha <-> riscv circular dependence We now split out the spike executable into another subproject, which depends on both rocket and hwacha	12 years ago