riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	b1dc3826d0	Don't error out if dlopen isn't available	6 years ago
Andrew Waterman	ac46e18f82	Raise virtual-instruction traps correctly for WFI/SRET/SFENCE	6 years ago
Andrew Waterman	fbb5a7620f	Fix polarity of hstatus.HU field	6 years ago
Andrew Waterman	d6ac560a1c	Don't throw virtual instruction exceptions for unimplemented CSRs	6 years ago
Han-Kuan Chen	3e7cba464d	rvv: fix int type is not enough to do shift (#544 ) int can only represent 32 bit in lp64 model when sew is greater than 32, the behavior is undefined	6 years ago
Andrew Waterman	a3376ff9af	Populate tval registers on illegal-/virtual-instruction traps	6 years ago
Andrew Waterman	8957a8efec	No need to catch illegal CSRs in set_csr get_csr is always called first (and this assumption is pervasively relied upon), so the checks in set_csr are redundant. FYI @avpatel	6 years ago
Abhinay Kayastha	58f23e111f	Add MIP_MEIP to all_ints (#543 )	6 years ago
Andrew Waterman	ecc87c4ce3	Merge pull request #542 from chihminchao/rvv-fix-2020-09-08 Rvv fix 2020 09 08	6 years ago
Chih-Min Chao	57fbf0eeb1	rvv: disasm: separate vvm and vv Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	f398f0af9b	rvv: disasm: fix vamoadd name Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Anup Patel	3101b47288	Fix MIDELEG and MEDELEG emulation when H-extension is available (#537 ) This patch does two fixes when H-extension is available: 1. The MEDELEG should allow delegating VIRTUAL_SUPERVISOR_ECALL instead of SUPERVISOR_ECALL. This was broken after commit `7775c6fb7c`. 2. The forced bits in MIDELEG should be cleared when 'H' bit is cleared in MISA CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com>	6 years ago
Andrew Waterman	f974ce1c6d	Merge pull request #535 from chihminchao/rvv-pre-1.0-2020-08-27 Rvv pre 1.0 2020 08 27	6 years ago
Chih-Min Chao	989f8772f3	rvv: reading vcsr needs to enable mstatus.vs Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	526b9abb7c	rvv: disasm: fix amo sub-opcode Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	52b3eb9380	rvv: disasm: fix whole load Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	6f7b46f71f	rvv: relax checking for vs1 vs1 is sub-op Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	69fcd8d2fe	rvv: trigger exp for illegal ncvt/wcvt eew Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	fa23a1cc1d	rvv: check invalid frm for floating operations Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	c9da294332	rvv: add reciprocal instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	eceda60356	softfloat: add reciprocal api Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	e11db4e6c9	rf: remove bit extraction from processor.h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	bfc2bead78	rvv: remove quad instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Tim Newsome	5f76a0d1fa	Fix debug tests failing with impebreak enabled. (#530 ) Introduced in #527.	6 years ago
Andrew Waterman	0f0fe6817e	Merge pull request #533 from chihminchao/rvv-fix-2020-08-20 rvv: fix vrgatherei16 overlap rule	6 years ago
Chih-Min Chao	30a741974a	rvv: fix vrgatherei16 overlap rule Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Andrew Waterman	6160ee9a94	mcounteren does not exist if U-mode is not implemented	6 years ago
Andrew Waterman	0ebb8a93b5	Merge pull request #527 from sobuch/optional-impebreak Add option to dissable implicit ebreak in program buffer	6 years ago
Samuel Obuch	5e073efff0	Add option to dissable implicit ebreak in program buffer	6 years ago
Andrew Waterman	da34b0eee4	Merge pull request #521 from chihminchao/op-hypvervisor Op hypvervisor	6 years ago
Andrew Waterman	99eab5eede	Merge pull request #520 from chihminchao/rvv-enhance-vstart Rvv enhance vstart	6 years ago
Chih-Min Chao	7775c6fb7c	op: hyperviosr: fix exception code and name Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	f5e4f0cf32	op: rearrange hypbervisor op/csr/cause The change comes from the generation order in riscv-opcodes. The original definition is placed in opcode-system but the new one is placed in separated opcode-rv64h and opcode-rv32h. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	6e4977abdb	rvv: add 'vstartalu" option to --varch arugment except for load/store instructions 0 : all instruction can't have non-zero vstart not 0 : all instruction can have non-zero vstart if it is not required vstart must be zero in spec the default value is 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	959700ec11	op: rvv: fix pesudo code instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Andrew Waterman	6859ccfa4a	Merge pull request #519 from chihminchao/rvv-pre-1.0 Rvv pre 1.0	6 years ago
Chih-Min Chao	5a107c6ba7	f16: fix Nan-Box macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	9fadb08893	rvv: fix frac_lmul get function Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	a4482608e8	rvv: remove isa string zvamoand zvlsseg Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	a602aa595c	rvv: remove veew/vemul state They aren't arch state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	cdda51cb0a	rvv: add vrgatherei16.vv Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	effb92a5ec	rvv: add new whole reg load/store instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	3075210b49	rvv: op: rearrange some instruction since generation order change Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	4d6086e094	rvv: op: fix amo naming The original name misses the 'i' in instruction mae vamoswape8 -> vamoswapei8 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	f2d6531ade	rvv: remove slen The command parser still can accept SLEN but the value is not stored in implementation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	fabc3c4484	rvv: initialize vector register as zero some dump and comparison tool may depennd the initial state of vector register. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	3784c3f681	rvv: disasm: fix missing vamoorei operands Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Andrew Waterman	6275cdf04d	Merge pull request #517 from riscv/rvv-1.0-vtype Incorporate RVV 1.0 vtype layout change	6 years ago
Andrew Waterman	308b6db549	Incorporate RVV 1.0 vtype layout change	6 years ago
Andrew Waterman	67b7edd027	Remove deprecated decoding of xor x0,x0,x0 Some UCB implementations once used this to represent a pipeline bubble. But this encoding is reserved for future standard HINT use. Resolves #503	6 years ago

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