riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	ab21eb0e4c	Merge pull request #2165 from FrancescoScappatura-Ax/dtb_discovery_feature DTB discovery feature	1 month ago
Francesco Scappatura	2c94ea431e	DTB discovery feature	1 month ago
Andrew Waterman	b8eacc25b8	Merge pull request #2232 from riscv-software-src/fix-2230 Disallow delegation of misaligned-fetch exceptions when IALIGN=16	2 months ago
Andrew Waterman	4adab496a2	Disallow delegation of misaligned-fetch exceptions when IALIGN=16 Fixes #2230	2 months ago
Andrew Waterman	875a7ee66a	Merge pull request #2228 from abejgonzalez/patch-2 Modify in_bits to check in_valid before accessing	2 months ago
Abraham Gonzalez	78762796e8	Modify in_bits to check in_valid before accessing Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>	2 months ago
Andrew Waterman	eb6586e3de	Merge pull request #2227 from riscv-software-src/fix-2221 Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind	2 months ago
Andrew Waterman	aea74cb694	Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind Fixes #2221	2 months ago
Andrew Waterman	98ccf030bb	Merge pull request #2221 from DymShanks/fix/vu-mode-sireg Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access	2 months ago
DymShanks	49d1d2a802	Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access	2 months ago
Andrew Waterman	7655ac0843	Merge pull request #2223 from riscv-software-src/fix-deps Regularize extension-dependency handling	2 months ago
Andrew Waterman	8b802199fb	Have Zabha imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	5c142baf88	Have ZC* imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	27ecd02d6b	Have Zvfofp4min imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	1a2af0362e	Clean up handling of Zcf	2 months ago
Andrew Waterman	ac939da203	Have V imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	466d1b0e4c	Have Z[v]fbfmin imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	8b22afdbd9	Have Zvfhmin imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	a91c0a9f51	Factor out add_extension method	2 months ago
Andrew Waterman	e9571d4498	Have Zfhmin imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	715906f416	Have Zclsd imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	978f96a992	Have Zicfiss imply extensions rather than erroring if not present	2 months ago
Andrew Waterman	9882cd202b	Zicfiss depends on Zaamo So, no need to check for Zaamo in the instruction definitions	2 months ago
Andrew Waterman	e7901f43aa	Don't log commits in snippy tests Doing so adds too much output to the CI logs.	2 months ago
Andrew Waterman	9cea90bd28	Merge pull request #2224 from riscv-software-src/add-vector-test Add simple vector extension test to CI	2 months ago
Andrew Waterman	52e6a75584	Echo CI commands to ease debugging	2 months ago
Andrew Waterman	6ff9d9ccd5	Add simple vector extension test to CI	2 months ago
Andrew Waterman	6dda4896cb	Merge pull request #2198 from riscv-software-src/fix-amocas-q Fix triggers for accesses wider than XLEN	2 months ago
Andrew Waterman	dfbd749842	Make reg_from_bytes a bit less gross I'd like to remove this routine eventually, but let's make it a bit less visually unappealing in the meantime.	3 months ago
Andrew Waterman	497e3d830d	DRY in logging code	3 months ago
Andrew Waterman	0f59a6dc75	Fix triggers for accesses wider than XLEN I believe that @en-sc's comment here is correct: https://github.com/riscv-software-src/riscv-isa-sim/pull/2161#discussion_r2564958203 Nevertheless, failing an assertion when someone sets a trigger on memory accessed by a wide access is not reasonable behavior for Spike. Better to do something that follows the principle of least surprise, despite the debug spec's lack of clarity on this point.	3 months ago
Andrew Waterman	b92958a9f1	Merge pull request #2216 from pointerliu/fix-tw-read csrs.cc: if no U-mode, mstatus.tw is read-only 0	2 months ago
pointerliu	4c10fbe07b	csrs.cc: if no U-mode, mstatus.tw is read-only 0	2 months ago
Andrew Waterman	efdaa08371	Merge pull request #2208 from riscv-software-src/remove-grevi Don't rely on definition of unratified bitmanip opcodes	3 months ago
Andrew Waterman	e532913fb3	Don't rely on definition of unratified bitmanip opcodes See https://github.com/riscv/riscv-opcodes/pull/401	3 months ago
Andrew Waterman	26aab67907	Clean up grevi/gorci/shfli/unshfli implementations No need for extra shamt variable.	3 months ago
Andrew Waterman	047b05cf7c	Merge pull request #2205 from Steven-Li-Xiaogang/master correct smcdeleg indirect CSRs address accessed via sireg*	3 months ago
steven	12e9a38efb	correct smcdeleg indirect CSRs address accessed via sireg*	3 months ago
Andrew Waterman	ce747bedbc	Merge pull request #2191 from Steven-Li-Xiaogang/master indirection CSRs 'iprio0~iprio15' are defined by Smaia/Ssaia extensions	3 months ago
Andrew Waterman	63c60931bc	Merge pull request #2204 from mmhus/mmhus/mireg-sireg-fixes Mmhus/mireg sireg fixes #2188, #2202, #2203	3 months ago
muhammad.moiz.hussain	49dea04810	fixed smcdeleg to be limited to, holds a value in the range 0x40-0x5F, from priv AIA section 9.1	3 months ago
muhammad.moiz.hussain	88783bf6e1	changed minstret to instret and mcycle to cycle	3 months ago
muhammad.moiz.hussain	2e7042897d	when AIA throw virt intruction exception and V=1 & vs-mode, otherwise throw illegal instruction exception	3 months ago
Andrew Waterman	59b2c834a4	Merge pull request #2193 from mslijepc/mslijepc_20251224_zicclsm added support for zicclsm	3 months ago
mslijepc	d6a5e90c40	removed cfg.misaligned option	3 months ago
Andrew Waterman	45fe6c110a	Merge pull request #2197 from omerguzelelectronicguy/master remove unnecessary dtb to dts operation	3 months ago
Andrew Waterman	1f92dadc89	Merge pull request #2161 from fkhaidari/fk/trig-algo-mod Update trigger behavior for memory accesses to match recommended debug specification behavior	3 months ago
Ömer Güzel	9b18d004f3	unnecessary dtb to dts operation removed	3 months ago
Farid Khaydari	06fd4d8526	Update trigger behavior for memory accesses to match recommended debug specification behavior According to the debug specification (select bit description): 0 (address): There is at least one compare value and it contains the lowest virtual address of the access. In addition, it is recommended that there are additional compare values for the other accessed virtual addresses match. (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 and the other addresses are 0x4001, 0x4002, and 0x4003.) 1 (data): There is exactly one compare value and it contains the data value loaded or stored, or the instruction executed. Any bits beyond the size of the data access will contain 0. Previously, when select bit was 0, Spike did not follow the recommendation and provided only 1 matching value to the trigger module. This change modifies the behavior to the recommended one. The implementation follows the debug specification recommendation. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>	4 months ago
Andrew Waterman	f0cc387904	Merge pull request #2194 from riscv-software-src/fix-2192 Remove declaration for undefined function	3 months ago

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3990 Commits (ab21eb0e4cade5c3daf9dd889a7bb77071f2c618) All Branches Search

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