Replace the long hard-coded extension dispatch chain in isa_parser.cc with
table-driven extension metadata. The table now records the extension name,
the extension bits it enables, direct implied extensions, and simple XLEN
requirements. This makes the parser behavior closer to LLVM, where
extension parsing and implication are represented as data rather than
as a large sequence of adhoc conditionals.
Move MISA single-letter extensions into the same table as multi-letter
extensions. The parser now expands `g` to `imafd`, validates that the base
extension is `i`, `e`, or `g`, and then lets the normal single-letter parsing
loop consume the base extension through the table. This also centralizes
common MISA implications such as `a -> zaamo,zalrsc`, `b -> zba,zbb,zbs`,
`d -> f`, `q -> d,f`, `c -> zca`, and `v -> zve64d,zvl128b`.
Model the Zve implication chain explicitly in the extension table
zve32f -> zve32x, f
zve32x -> zicsr, zvl32b
zve64d -> zve64f, d
zve64f -> zve32f, zve64x
zve64x -> zve32x, zvl64b
v -> zve64d, zvl128b
Keep the Spike-specific Zve state updates out of the table by deriving
VLEN, ELEN, zvf, and zvd from the Zve extension name in a small helper.
Add a separate combine pass for reverse combination rules that reconstruct
combined extension bits from their component bits. This keeps combine logic
separate from forward implication while preserving existing Spike behavior:
zaamo + zalrsc -> A
zba + zbb + zbs -> B
C + D -> Zcd
Zicfiss + Zca -> Zcmop
Retain explicit Spike-specific post-parse checks and derived state where they
remain clearer than table entries, including RV32-only `C/Zce + F -> Zcf`,
`Zfbfmin/Zfhmin -> EXT_INTERNAL_ZFH_MOVE`, incompatibility checks, privilege
mode handling, and VLEN limit validation.
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Replace bare __int128 / unsigned __int128 in psshar_dhs.h and psshar_dws.h
with the int128_t / uint128_t typedefs from fesvr/byteorder.h, and guard
the entire riscv_insn_ext_p list in riscv.mk.in with $(if $(HAVE_INT128),...)
matching the existing pattern for the V extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Per the P-extension spec, any instruction that performs saturation must
set the vxsat CSR to 1 when the result is clamped. 70 instructions were
missing this write, addressed here in two ways:
1. Convert P_SAT, P_USAT, and P_USAT_FULL macros from pure expression
macros to GCC statement expressions that detect when saturation
occurs and write P.VU.vxsat. This automatically fixes ~42
instructions that use these macros (nclip/nclipi/nclipr/nclipri
families, psati, psslai, pssh1sadd, pusati, sati, usati, ssh1sadd,
sslai, and their packed/double-wide variants).
2. Add explicit vxsat writes to 22 instructions with inline saturation
logic that bypasses the macros:
- mulq/mulqr/pmulq/pmulqr: set vxsat on INT_MIN * INT_MIN overflow
- psas/pssa cross variants: set vxsat from sat_add/sat_sub sat flag
- pssha/psshar DW variants: set vxsat from ov overflow flag
- pssha/psshar/ssha/sshar: set vxsat in sshamt >= BIT overflow path
- pusati_dh/pusati_dw: set vxsat on unsigned range clamping
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Bulk normalized dot product is expected to raise the invalid flag if two products with infinite values and opposite signs are added.
Spike function failed to consider the second operand of a product when determining whether the product had infinite value or not, and missed the exclusion of NaN and zero from this case.
The zero case is quiet, because it happens for inf * zero which is expected to raise the invalid flag. The qNaN case is not quiet and can cause the apparition of a spurious invalid flag when none were expected.
Jerry Zhang Jian
Andrew Waterman
Chih-Min Chao
Natheir Abu-Dahab
Vladimir Efimov
demin.han
Jason
Alexander Romanov
Nicolas Brunie
nabudahab
Hasmet Akgun
cst-saswatm
Zhibo Hong
Binno Shen
Michelle Wu
Hiroo HAYASHI