riscv
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riscv-isa-sim
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3 Commits (a68d310bcb066c031ce9121fabefc9ca6c8c8f80)

Author SHA1 Message Date
Weiwei Li a68d310bcb Bind disas for instructions with the isa support
4 years ago
Weiwei Li d685520fed Use unified ISA-string processing in spike-dasm and spike
4 years ago
Andrew Waterman 59d450e586 Separate build of spike and spike-dasm
6 years ago
Andrew Waterman bb1cd8f9e3 Decouple spike-dasm program from simulator code
6 years ago
Andrew Waterman 8ffefbc9a1 Add --priv option to control which privilege modes are available
6 years ago
Chih-Min Chao 48fe0c484d rvv: add varch option parser and initialize vector unit
7 years ago
Andrew Waterman aff796dbf6 Handle spike-dasm inputs with leading 0x correctly
8 years ago
Andrew Waterman 03b8bad375 Disassemble RVC instructions based on XLEN
10 years ago
Yunsup Lee 9af855a28e correctly parse extension for spike-disasm
11 years ago
Andrew Waterman d8022e9eda properly sign-extend instructions in spike-dasm
11 years ago
Andrew Waterman 17fd25f267 Rename riscv-dis to spike-dasm
11 years ago
Andrew Waterman 416c8be88c Support building from within root directory
11 years ago
Andrew Waterman d643e43dca Support 2/4/6/8-byte instructions
11 years ago
Andrew Waterman 590417bec9 Factor out the dummy RoCC accelerator
12 years ago
Scott Beamer 0ac8a9b068 clean up warnings from clang
12 years ago
Yunsup Lee 0a048a93eb add extensions to riscv-dis for better disassembly
12 years ago
Yunsup Lee cb6cfc5f3a refactor disassembler, and add hwacha disassembler
13 years ago
Andrew Waterman 620d8bc0fe Add helper disassembly program
13 years ago