riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Weiwei Li	a68d310bcb	Bind disas for instructions with the isa support	4 years ago
Weiwei Li	d685520fed	Use unified ISA-string processing in spike-dasm and spike	4 years ago
Yueh-Ting (eop) Chen	4557eef700	Add more assertion for fcvt (#910 )	4 years ago
Andrew Waterman	eb53d231f5	Merge pull request #908 from plctlab/fix-redifinition-csrs fix redefinition of CSR_MCONTEXT and CSR_SCONTEXT	4 years ago
Weiwei Li	78ee489d5a	fix redefinition of CSR_MCONTEXT and CSR_SCONTEXT	4 years ago
Andrew Waterman	3482790b26	Fix HINVAL.VVMA and HINVAL.GVMA opcodes The opcodes were incorrect in riscv-opcodes; now they match the spec.	4 years ago
Andrew Waterman	e93b9cbbbc	Merge pull request #899 from riscv-software-src/rv32e Add RV32E/RV64E base ISA support	4 years ago
Andrew Waterman	d1a3a42552	Changes to be cleaner wrt. -Wextra h/t @jerinjoy See #901	4 years ago
Andrew Waterman	fc572daaef	Support RV32E/RV64E base ISAs	4 years ago
Andrew Waterman	2fbc6cde0b	Parse RV32E/RV64E base ISA strings; improve error messages	4 years ago
Andrew Waterman	94381783d6	DRY in illegal-instruction descriptors	4 years ago
Andrew Waterman	5b7cdbe1cf	DRY in selecting instruction functions	4 years ago
Tim Newsome	39fc8c3921	Don't say "master" (#898 ) Requested by "LfX Security - Non Inclusive Language Alerts"	4 years ago
Andrew Waterman	336a5813fd	Disassemble Zbs instructions	4 years ago
Yueh-Ting (eop) Chen	d750d6a92b	Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896 ) Refer to rvv-spec v1.0-rc2	4 years ago
Yueh-Ting (eop) Chen	cfcf083a8f	Fix check for fcvt (#897 )	4 years ago
Yueh-Ting (eop) Chen	f858b9054f	Fix check for fcvt (#894 )	4 years ago
Yueh-Ting (eop) Chen	8219bf0baa	Add missing check for floating-point merge instructions (#893 )	4 years ago
Tsukasa #01 (a4lg)	f1ca8de721	Add disassembler support for `unimp' (#886 ) Now it disassembles 0x0000 (invalid encoding of c.addi4spn) as c.unimp (RVC). Non-RVC variant of unimp pseudoinstruction (0xc0001073) is also implemented.	4 years ago
Andrew Waterman	6751b49ac1	Merge pull request #881 from eopXD/simplify-float-convert Simplify float convert instructions	4 years ago
Andrew Waterman	f1a6fb9695	Now on 1.1.1-dev	4 years ago
Andrew Waterman	530af85d83	1.1.0 release	4 years ago
sven	d1f2019ec1	TSR is read-only 0 when S-mode is not supported. (#890 ) According the privileged spec, TSR is read-only 0 when S-mode is not supported. (`56515289e5/src/machine.tex (L860-L861))`	4 years ago
Yueh-Ting (eop) Chen	0f30988e4d	Fix minor type-o (#885 )	4 years ago
marcfedorow	7953ae6603	P-ext v.0.9.11. update (#883 )	4 years ago
Yueh-Ting (eop) Chen	65ef13629a	Simplfy vfmv_v_f (#884 )	4 years ago
eopXD	f25933a483	Simplify vfwcvt	4 years ago
eopXD	76bc15ad4b	Simplfy vfcvt	4 years ago
eopXD	95c06fbc24	Simplify vfncvt	4 years ago
eopXD	381b28d634	Have vd.v unexposed	4 years ago
Tsukasa #01 (a4lg)	a68c7b12e6	Add 'Zfhmin' extension (#880 ) Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating point) extension, consisting only of data transfer and conversion instructions. This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin" as a multi-letter extension and adjusts feature gate for data transfer / conversion instructions. * FLH / FSH * FMV.X.H / FMV.H.X * FCVT.S.H / FCVT.H.S * FCVT.D.H / FCVT.H.D (if 'D' extension is also present) * FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)	4 years ago
Andrew Waterman	9b3b305e42	Merge pull request #879 from eopXD/simply-insts Simply floating point parameters and merge operations	4 years ago
Yueh-Ting (eop) Chen	8f16ed328f	Simplify vadc and vsbc (#876 )	4 years ago
Andrew Waterman	522d8a20b7	Merge pull request #868 from eopXD/simplify-narrowing-inst Simplify narrowing instruction	4 years ago
Yueh-Ting (eop) Chen	49289b07b4	Simplify vwmulsu_vv and vwmulsu_vx (#861 ) Leverage macro VI_WIDE_OP_AND_ASSIGN_MIX	4 years ago
eopXD	1f06e0ecaa	Simplify vmerge, vfmerge	4 years ago
eopXD	626fce2075	Simplify floating point compare instructions	4 years ago
eopXD	278a7dd434	Simply parameters for floating-point instructions	4 years ago
Yueh-Ting (eop) Chen	9f18486669	Simplify vmadc and vmsbc (#877 )	4 years ago
John Ingalls	7209834847	page fault when PTE_N bit set and not EXT_SVNAPOT (#875 )	4 years ago
John Ingalls	c4fdc8fe95	page fault when PTE_PBMT bits set and not EXT_SVPBMT (#874 )	4 years ago
Andrew Waterman	a9b3babb8f	Merge pull request #871 from a4lg/string-handling Improve string handling (ISA string)	4 years ago
Tsukasa OI	a00445c8e0	Parse isa_string as C-style string On C++11 and later, std::string is guaranteed to be null-terminated. However, `*(str.end())` is NOT guaranteed to be '\0'. So, we parse ISA string using C-style string buffer (raw pointers).	4 years ago
Tsukasa OI	375d55ef44	Use strtolower in parse_varch_string	4 years ago
Yueh-Ting (eop) Chen	6507ccc30f	Simplify mulhsu (#870 )	4 years ago
Andrew Waterman	2b261c9782	Merge pull request #869 from scottj97/badgpa Take guest page fault if guest PA out of bounds	4 years ago
Andrew Waterman	6b0f6f46ee	Revert "Simplify vmulhsu (#863 )" This reverts commit `1a5b2d9dda`, which is buggy (the vs1 argument is being sign-extended).	4 years ago
Scott Johnson	f5dd47acbf	Reindent s2xlate()	4 years ago
Scott Johnson	22e97db4c4	Raise guest page fault if GPA is out of range Based on this statement from priv spec 5.5.1 (regarding Sv39x4): "Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs."	4 years ago
eopXD	d177f05b7b	Have nclip_{wv/wx/wi} use different macros This allows them to share PARAM macro with narrowing right-shift instructions. Rename VV_NSHIFT_PARAMS -> VV_NARROW_PARAMS so nclip, nsra, nsrl can share it. (Same goes to VX_NSHIFT_PARAMS and VI_NSHIFT_PARAMS)	4 years ago

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2000 Commits (a68d310bcb066c031ce9121fabefc9ca6c8c8f80) All Branches Search

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