Tree: a515bc5205

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-2296

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

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Commit Graph

4026 Commits (a515bc5205be023ab01d047afc4085676a328ee2)

 

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Author	SHA1	Message	Date
Andrew Waterman	a515bc5205	Remove extraneous comment	1 month ago
Andrew Waterman	0ad45926ac	Merge pull request #2265 from bwv846/mop_rr_7 Fix duplicate addition of mop_rr_7	1 month ago
Hasmet Akgun	80a1c934d4	Fix duplicate addition of mop_rr_7	1 month ago
Andrew Waterman	5eeeb91efa	Merge pull request #2263 from CircuitSutra/fix_dts_compile_api_hang Fixed dtc_compile API hangs as child process waits to perform "exit()" instead of "_exit()".	1 month ago
cst-saswatm	276be7383b	updated child process exit to _exit	1 month ago
Andrew Waterman	a6fb7578c9	Merge pull request #2261 from riscv-software-src/fix-bulk-norm Bulk normalization granularity is based on VLMAX, not vl	1 month ago
Andrew Waterman	108cf836cb	Bulk normalization granularity is based on VLMAX, not vl	1 month ago
Andrew Waterman	170f398cd4	Merge pull request #2251 from hirooih/make-the-executable-path-relative-from-spike make the executable path relative from spike	1 month ago
Andrew Waterman	509bec19b0	Merge pull request #2253 from 5265325/feat/zvzip Add Zvzip extension.	2 months ago
Zhibo Hong	848474582d	Add Zvzip extension.	2 months ago
Andrew Waterman	204b88deda	Merge pull request #2255 from binno/rvv_crypto_fix disasm: Do not imply Zvbb from RVV crypto groups (#146)	2 months ago
Binno Shen	cd58db2ba7	Merge branch 'master' into rvv_crypto_fix	2 months ago
Andrew Waterman	e6b1a9df4e	Merge pull request #2254 from 5265325/feat/svvptc Add Svvptc extension.	2 months ago
Michelle Wu	e06eae1039	disasm: Do not imply Zvbb from RVV crypto groups (#146) Remove EXT_ZVBB enablement from Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvksg • Zvkn = Zvkned + Zvknhb + Zvkb + Zvkt • Zvknc = Zvkn + Zvbc • Zvkng = Zvkn + Zvkg • Zvks = Zvksed + Zvksh + Zvkb + Zvkt • Zvksc = Zvks + Zvbc • Zvksg = Zvks + Zvkg	2 months ago
Zhibo Hong	38f162ccd0	Add Svvptc extension.	2 months ago
Hiroo HAYASHI	b386d87922	make the executable path relative from spike If the relative path cannot be found, use the current PREFIX. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>	2 months ago
Andrew Waterman	76ced61f54	Merge pull request #2209 from 5265325/feat/zvabd Add Zvabd extension.	2 months ago
Zhibo Hong	3bfe3ce5ee	Add Zvabd extension.	6 months ago
Andrew Waterman	5968cbe53e	Merge pull request #2242 from Steven-Li-Xiaogang/master fix M-mode access scountovf according to Sscofpmf Version V1.0	2 months ago
steven	926d1c01d8	fix M-mode access scountovf according to Sscofpmf Version V1.0	2 months ago
Andrew Waterman	591cff1610	Merge pull request #2207 from riscv-software-src/fix-2206 Only set mstatus.VS for legal vector instructions	3 months ago
Andrew Waterman	a437348306	Retire dirty_vs_state macro Reduce chance that it gets misused again in the future.	3 months ago
Andrew Waterman	a665eb0337	Don't write vstart in set_vl All callers (the vector_unit constructor and the vsetvl instructions) already initialize or otherwise zero vstart.	3 months ago
Andrew Waterman	ea29ce276c	Make sure VS is set on fault-only-first loads in all cases We weren't setting it in the case that an exception was detected on element 0, which is technically OK since no state changed, but is inconsistent with how we handle regular vector loads.	3 months ago
Andrew Waterman	17682e173d	Make all vector ALU instructions invoke VECTOR_END, dirtying VS dirty_vs_state is therefore no longer needed at the top in require_vector. Furthermore, the vstart write in VECTOR_END dirties VS, so dirty_vs_state is not needed.	4 months ago
Andrew Waterman	e8e3a747d5	Dramatically simplify whole-register loads/stores This makes the vstart/VS handling identical to regular vector loads/stores	3 months ago
Andrew Waterman	ae1531c207	Merge pull request #2239 from riscv-software-src/fix-2238 Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate	3 months ago
Andrew Waterman	114be91bbe	Remove incorrect use of static variable It prevents modeling mixed RV32/RV64 systems.	3 months ago
Andrew Waterman	0714f0f588	Simplify masking of mnstatus bits when H is toggled	3 months ago
Andrew Waterman	6aa146d209	Simplify masking of medeleg bits when H is toggled	3 months ago
Andrew Waterman	cdca6411ad	Simplify masking of mhpmevent bits when H is toggled	3 months ago
Andrew Waterman	1d50ad3984	Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate	3 months ago
Andrew Waterman	68d4514685	Merge pull request #2236 from riscv-software-src/fix-2235 Don't error out if program buffer has size 0	3 months ago
Andrew Waterman	c73c3a1791	Merge pull request #2234 from hirooih/README.md-gdb-semihosting Updated “Debugging With Gdb” to use semihosting	3 months ago
Andrew Waterman	ab21eb0e4c	Merge pull request #2165 from FrancescoScappatura-Ax/dtb_discovery_feature DTB discovery feature	3 months ago
Andrew Waterman	5564ca81b7	Don't error out if program buffer has size 0 Resolves #2235	3 months ago
Hiroo HAYASHI	82742081e9	Updated “Debugging With Gdb” to use semihosting - make the sample program as a typical C program that uses the stack and semihosting (#155). - use the default crt0.o and linker script. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>	2 years ago
Francesco Scappatura	2c94ea431e	DTB discovery feature	3 months ago
Andrew Waterman	b8eacc25b8	Merge pull request #2232 from riscv-software-src/fix-2230 Disallow delegation of misaligned-fetch exceptions when IALIGN=16	3 months ago
Andrew Waterman	4adab496a2	Disallow delegation of misaligned-fetch exceptions when IALIGN=16 Fixes #2230	3 months ago
Andrew Waterman	875a7ee66a	Merge pull request #2228 from abejgonzalez/patch-2 Modify in_bits to check in_valid before accessing	3 months ago
Abraham Gonzalez	78762796e8	Modify in_bits to check in_valid before accessing Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>	3 months ago
Andrew Waterman	eb6586e3de	Merge pull request #2227 from riscv-software-src/fix-2221 Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind	3 months ago
Andrew Waterman	aea74cb694	Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind Fixes #2221	3 months ago
Andrew Waterman	98ccf030bb	Merge pull request #2221 from DymShanks/fix/vu-mode-sireg Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access	4 months ago
DymShanks	49d1d2a802	Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access	4 months ago
Andrew Waterman	7655ac0843	Merge pull request #2223 from riscv-software-src/fix-deps Regularize extension-dependency handling	4 months ago
Andrew Waterman	8b802199fb	Have Zabha imply extensions rather than erroring if not present	4 months ago
Andrew Waterman	5c142baf88	Have ZC* imply extensions rather than erroring if not present	4 months ago
Andrew Waterman	27ecd02d6b	Have Zvfofp4min imply extensions rather than erroring if not present	4 months ago