21458a2710
rvv: index load/store have benn separated into ordered and unordered parts ( #611 )
ref:
511d0b84a3
6 years ago
654480447f
Remove stray comma in configure
6 years ago
0cb148a051
Fix Issue #609 ( #610 )
Fix Issue #609 where extraneous debugging output was added when the user
invoked any simulation operation that involved addr_to_mem.
6 years ago
f4f6e12eee
Fix #607 : Add a core parameter to the interactive str command ( #608 )
Add a core parameter to the interactive str command. This makes it
possible for the spike user to specify the device whose memory contains
the NUL-terminated string to be printed.
6 years ago
4b04d71529
Merge pull request #605 from avpatel/riscv_gva_fix_v1
Fix hstatus.GVA and mstatus.GVA updation
6 years ago
d0d923ebde
Fix typo in HTVAL CSR write emulation
We are saving new HTVAL value in wrong location for HTVAL CSR write
so let's fix this.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
6 years ago
457f628ad7
Fix hstatus.GVA and mstatus.GVA updation
The hstatus.GVA and mstatus.GVA should be set only when guest virtual
address is written to stval or mtval CSRs at time of taking trap.
This patch update access, page fault, and guest page fault trap classes
so that we can pass gva flag correct from source of the trap.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
6 years ago
d6cf0d2363
Include stdexcept in ELF loader ( #603 )
6 years ago
a73e43f231
Fix misaligned loads and stores for big endian target ( #602 )
6 years ago
8be5c086bd
Fix VSSTATUS bits updation ( #568 )
This patch fixes VSSTATUS bits updations as follows:
1. set_csr() should not allow writs to VSSTATUS.SD bit instead
VSSTATUS.SD bit should be derived again after VSSTATUS is updated
2. set_virt() should copy FS, VS and XS bits when transitioning
from virt=on (VS/VU-mode) to virt=off (HS/M-mode)
Signed-off-by: Anup Patel <anup.patel@wdc.com>
6 years ago
e2e83c0604
Don't include PTE.N bit as part of the PPN
6 years ago
ec00b9bc69
Invalid NAPOT settings cause page faults, not access exceptions
6 years ago
fce242a5d4
Add Zsn extension
h/t @daniellustig
6 years ago
081bcaddc5
Avoid use of __builtin_popcount for portability
6 years ago
b2a2f24692
Avoid use of __builtin_ctz for portability
6 years ago
29178e659d
Avoid use of __builtin_bswap for portability
I verified the new versions still compile to efficient x86 code (rolw/bswap[q])
6 years ago
a081a013f3
Only use __builtin_expect for __GNUC__
6 years ago
a4994cba0d
Fix byteorder issues with struct riscv_stat ( #596 )
6 years ago
77d84472c9
Merge pull request #598 from chihminchao/pmp-per-core
Pmp per core
6 years ago
b4aa36c4ba
dts: config pmp attribute by each core's setting
The original implementation only uses the value in first core and apply it
to other core. The patch makes the configuration hetergeneous for differenct
cores.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
0ca970dce3
dts: extract cpu node checking as helper function
all atrribute in cpu could leverage it
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
70fdec9e63
Correct AMO exception cause for misaligned accesses ( #594 )
Broken by 91092f21948ba2e77bfbc4629b82b6aa14d5ed6
6 years ago
828d8553dc
Merge pull request #592 from scottj97/fix-misaligned-lr
Fix LR missing misaligned exception
6 years ago
9380375e22
Merge pull request #593 from chihminchao/selective-mmu-mode
Selective mmu mode
6 years ago
b675e0af5b
dts: mmu: parse mmu-type in dts
1. setup allowed mmu-type from dts
2. change default mmu-type in dts from sv39 to sv48
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
0481b56f34
dts: extend dts api to get info of each cpu
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
bed716c601
mmu: check mmu support
if no mmu
1. mask TVM and VTVM
2. wire satp and vsatp as 0
3. disable sfence_vma
4. allow only supported type
5. mask SUM/MXR
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
51b5702b69
mmu: extract common part of satp and vsatp setting
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
ad8ef88a22
mmu: add impl table and set function
some features are optional to u-arch or could be selectively supported.
Add an impl_table to keep implemented feature
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
e91092f219
Use new require_alignment flag to simplify AMO check
6 years ago
f019910e12
Make LR properly take misaligned exception
Fixes https://github.com/riscv/riscv-isa-sim/issues/591
6 years ago
956ef9ac3a
Update readme to reflect bi-endian support
6 years ago
6fe352d543
Merge pull request #575 from zeldin/big-endian
Big endian target support
6 years ago
ad9bbf1994
Make mmu_t::target_big_endian always available
This allows some #ifdefs to be removed. When compiling without
--enable-dual-endian, target_big_endian is a static constant,
allowing the compiler to optimize away the dead branches.
6 years ago
212249e7c0
Allow fixed endianness to be observed through MBE/SBE/UBE
6 years ago
8e3bcb2eef
Tag target endian values to help guide conversion code
6 years ago
ec2fd09fdb
Update generated configure script
6 years ago
8d09d845a7
Implement support for big-endian targets
6 years ago
641d7d03e6
Merge pull request #588 from kito-cheng/master
doc: update readme for bitmanip 0.92
6 years ago
2a9849e3ab
doc: update readme for bitmanip 0.92
6 years ago
1d30acb2d4
Merge pull request #586 from chihminchao/rvv-fix-2020-10-26
Rvv fix 2020 10 26
6 years ago
30a45bb89c
rvv: check extra dst for index segment load
each segment register group has to follow overlapping rule
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
1af67080dd
commitlog: fix compilation warning
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 years ago
b2b6f45c15
Validate integer command-line arguments
Resolves #583
6 years ago
47e17aa074
Merge pull request #582 from avpatel/riscv_s2xlate_trap_fix_v1
s2xlate() trap fix
6 years ago
414c471c14
Fix trap generation in s2xlate()
The G-stage traps generated while doing VG-stage page table walks
should be based on original access type. This patch fixes s2xlate()
accordingly.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
6 years ago
ec6ded4f2f
Merge pull request #580 from riscv/riscv-bitmanip
Incorporate draft B extension
6 years ago
a06446f29d
Swap MAX and MINU encodings
6 years ago
d286140afe
Remove subu.w; change addu.w definition
6 years ago
cab796f546
Start adding B ext to disassembler
6 years ago
Chih-Min Chao
Andrew Waterman
Will Hawkins
Anup Patel
Daniel Bates
Marcus Comstedt
Chih-Min Chao
Scott Johnson
Kito Cheng