- Reverts the AES32 and SM4 instruction encodings back to a normal R-type
encoding, per the advice of the architecture reviewers.
On branch scalar-crypto-v0.9.2
Changes to be committed:
modified: riscv/encoding.h
modified: riscv/insns/aes32dsi.h
modified: riscv/insns/aes32dsmi.h
modified: riscv/insns/aes32esi.h
modified: riscv/insns/aes32esmi.h
modified: riscv/insns/sm4ed.h
modified: riscv/insns/sm4ks.h
problem:
when the following memory region is specified
-m0x00410000:0x1000,
0x00410200:0x1000,
0x00410400:0x1000,
0x00410600:0x1000,
0x00410800:0x1000,
0x00411000:0x1000,
0x00412000:0x1000,
0x00413000:0x1000,
0x00414000:0x1000
The error is
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR (duplicate_node_names): Duplicate node name /memory@410
ERROR: Input tree has errors, aborting (use -f to force output)
cause:
the merge_overlapping_memory_regions works not well in partial overlap case
change:
1. use forward way to avoid weird reverse iterator behavior in C++
2. use address but not page number since the base addresses are
all aligned in make_mems
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
After the privilege draft-20191120-569d071, the section 3.1.6.3 says
"An MRET or SRET instruction that changes the privilege mode to
a mode less privileged than M also sets MPRV=0.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
With recent compilers on recent computers, the much simpler version of
the code is actually slightly faster. I suspect, but haven't proven,
that more accurate indirect jump prediction is the main explanation.
Reduced I$ pressure might be a secondary factor.
At compile time, gcc complains with:
../riscv/processor.cc:787:94: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 5 has type ‘uint64_t {aka long unsigned int}’ [-Wformat=]
The variable 'bits' is an uint64_t, so that PRIx64 should be used to print it out.
* Implement JTAG BYPASS register.
This allows spike to put into a virtual scan chain with other
remote_bitbang JTAG devices.
* Initialize bypass to 0.
Also change what we do on what edge. In theory that's more correct but
in practice it doesn't make a difference.
* make value display depend on max_xlen
* try to make spike look for correct pk
* PRIx64 instead of PRIx32, TARGET_ARCH back to 64
* 32 bit memory data, exception epc and tval
We can use the nullness of pointers to indicate RV32-only or RV64-only
instructions, rather than a new field dedicated to that purpsoe.
The bug fix is that the new field wasn't always initialized; now,
it doesn't need to be.
Resolves#673
Otherwise, mstatus.MPV and hstatus.SPV could remain 1, and executing
mret/sret would then set state.v=1, which would be bad since
hypervisor's supposed to be disabled.
* Simplify Boolean logic
No functional change intended.
* Apply same logic to virtualize sstatus.XS as used for VS and FS
Though this macro does not seem to be used anywhere today.
* Extract common macro to DRY up code
* Dirty both mstatus and vsstatus FP fields
Fixes https://github.com/riscv/riscv-isa-sim/issues/660
Andrew Waterman
Ben Marshall
Chih-Min Chao
sven
ChunPing Chung
jmonesti
Tim Newsome
emelcher
Allen Baum
marcfedorow
huaixv
Scott Johnson
jameshippisley
francis4096