riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Chih-Min Chao	7b060d0d86	disasm: show the acquire and release attribute to amo instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	10 months ago
Chih-Min Chao	e2e02098a4	ext: add zibi It implement v0.6 version reference https://github.com/riscv/zibi/releases/download/v0.6/zibi.pdf https://riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	10 months ago
Andrew Waterman	3232ce1b76	Implement Zvflqdot8f	10 months ago
Andrew Waterman	e3dc14a878	Implement Zvfbqdot8f	10 months ago
Andrew Waterman	1d56b556b5	Relax VLEN/ELEN checking We should allow ISA strings like rv64gc_zve32f. Per the spec, the various Zve extensions imply a minimum VLEN, so rv64gc_zve32f is unambiguously equivalent to rv64gc_zve32f_zvl32b. Similarly, rv64gc_zve64x, rv64gc_zve64x_zvl64b, and rv64gc_zve64x_zvl32b are all unambiguously equivalent.	11 months ago
Andrew Waterman	faeae4eada	VLEN is unitless	11 months ago
Andrew Waterman	acac77d59d	No tabs	11 months ago
Andrew Waterman	717a6e275c	Add Zvldot extension support	11 months ago
Nadime Barhoumi	dcb5f0c784	Remove redundant checks in Zfbfmin and Zvfbfmin validation	11 months ago
Nadime Barhoumi	715c1597ab	Fix BFloat16 vector extension dependencies * Enable EXT_INTERNAL_ZFH_MOVE when either Zfbfmin or Zfhmin is enabled * Change Zvfbfmin to require Zve32f instead of V extension. * Add proper dependency chain for Zvfbfwma requiring both Zvfbfmin and Zfbfmin.	12 months ago
Nado15	23ad840e4d	Add VLEN < ELEN validation check	1 year ago
Andrew Waterman	dd4d3fbca9	Implement Zvbdot draft	1 year ago
Hao	9950cb3d59	fix: check ext_str size when ext = zve* `zve` = "zve{32, 64}{x, f, d}", size of `zve` must be 6. Signed-off-by: Hao <58808837+ha0lyu@users.noreply.github.com>	1 year ago
Andrew Waterman	cce834e437	Support Ziccid extension	1 year ago
Andrew Waterman	b6a061b683	Support Ziccif extension	1 year ago
YenHaoChen	d4abc9a71b	AIA: Enable Smcsrind/Sscsrind if supporting Smaia/Ssaia Smaia/Ssaia allocates indirect CSRs 0x30~0x3f for major interrupt priorities and 0x70~0xff for external interrupts (only with an IMSIC).	2 years ago
YenHaoChen	8050278445	AIA: Add isa=..._smaia_ssaia_... option	2 years ago
Muhammad Moiz Hussain	4764d3c029	Implement Ssccfg & Smcdeleg for spike Signed-off-by: muhammad.moiz.hussain@semidynamics.com	1 year ago
Mingzhu Yan	4d3920b262	Add Svade extension Support Spike always supports the Svade extension, this is required by the RVA and RVB profiles	1 year ago
Andrew Waterman	b645cc0fba	Explicitly annotate fallthrough cases (-Wextra)	1 year ago
Andrew Waterman	8ccde08b27	Remove unused functions (-Werror)	1 year ago
Mahmoud Abumandour	cfa593d0ea	isa_parser: don't append one char at a time in strtolower This avoids potential re-alloations as it allocates the result string upfront.	1 year ago
Andrew Waterman	5ed426bbf4	Add Zvqdotq extension Not yet frozen, but in a pretty stable state. See https://github.com/riscv/riscv-dot-product	1 year ago
Andrew Waterman	1e589aa502	Support strict disassembly in disassembler_t	2 years ago
Christian Herber	ff771919ec	Updated load/store pair for RV32 to v0.10 - renamed Zcmlsd to Zclsd - bumped version number	2 years ago
Andrew Waterman	9a641bb03e	Validate Zvl ISA string correctly See #1810 for explanation of how this can go wrong. Resolves #1810	2 years ago
Andrew Waterman	6b74bd669d	Validate Zvl ISA string correctly See #1810 for explanation of how this can go wrong. Resolves #1810	2 years ago
Jerry Zhao	b47080fea4	Remove --with-priv compile flag	2 years ago
YenHaoChen	6a1a5db16b	vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions	2 years ago
YenHaoChen	b47d0baab3	vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single-width floating-point fused multiply-add instructions	2 years ago
YenHaoChen	7f38a503d0	vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions	2 years ago
YenHaoChen	ff62109211	vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single-width integer multiply-add instructions	2 years ago
Jerry Zhao	9031c7b651	Fix ordering of B single-letter extension The canonical order is IMAFDQLCBKJTPVH Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>	2 years ago
Ved Shanbhogue	c302e8bd16	Add Smdbltrp	2 years ago
Ved Shanbhogue	0797c21001	Add Ssdbltrp	2 years ago
YenHaoChen	370f741a97	pointer masking: Support _ssnpm to --isa	2 years ago
YenHaoChen	eea20ae6a2	pointer masking: Support _smnpm to --isa	2 years ago
YenHaoChen	436b684ff5	pointer masking: Support _smmpm to --isa	2 years ago
Andrew Waterman	6854a911fd	Expand default disassembly ISA	2 years ago
Andrew Waterman	389851ce15	Add disassembly for Zfa extension	2 years ago
Rafael Sene	ef7416ce1d	Fix: Add missing <stdexcept> header for std::logic_error - Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'. Signed-off-by: Rafael Sene <rafael@riscv.org>	2 years ago
Jerry Zhao	67e205c289	Restrict spike to vlen <= 4096	2 years ago
Jerry Zhao	457ea8c0cd	Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve	2 years ago
Jerry Zhao	9925435513	Allow disassembly from implementations that are not full V	2 years ago
Jerry Zhao	ede537120b	Add Zvl/Zve validation to isa_parser	2 years ago
Jerry Zhao	0408e797b1	Add isa_parser parsing for zvl/zve	2 years ago
Andrew Waterman	c6cb05ceb7	In isa_parser, move extensionology code before error-checking code Resolves #1696	2 years ago
Christian Herber	70d26d64e6	Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32)	2 years ago
Ved Shanbhogue	c5229c3f5f	Add Zawrs extension	2 years ago
Andrew Waterman	c4edeabbe7	Remove P, Zbpbo, Zpn, and Zpsfoperand from ISA parser	2 years ago

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148 Commits (9b136d0210f87fb73244909ae8a207a1095d105f)