Albert Ou
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826fc1719a
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Implement "half-baked" half-precision instruction subset for Hwacha
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13 years ago |
Andrew Waterman
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c8a8c07ec2
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Use WRITE_RD/WRITE_FRD macros to write registers
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13 years ago |
Andrew Waterman
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77452a26e7
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temporary undoing of renaming
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15 years ago |
|
Andrew Waterman
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740f981cfd
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[sim] renamed to riscv-isa-run
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15 years ago |
Andrew Waterman
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6928933df6
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[sim] fixed fcvt rounding bugs
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15 years ago |
|
Andrew Waterman
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f0063c2e8b
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[sim, pk, xcc, opcodes] great instruction renaming of 2011
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16 years ago |
|
Andrew Waterman
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21ce327f5d
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[opcodes, sim, xcc] made *w insns illegal in RV32
now generic variants behave differently in RV32 and RV64.
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16 years ago |
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Andrew Waterman
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259d20a35d
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[opcodes, pk, sim, xcc] Tweaked FP encoding
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16 years ago |
|
Andrew Waterman
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7471eee0ba
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[xcc, sim, pk, opcodes] new instruction encoding!
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16 years ago |
|
Andrew Waterman
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2c9a832352
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[sim,xcc,pk,opcodes] static rounding modes for FP insns
Now, you can either use the RM in the FSR or specify it in the insn.
(Except for FP->int; no dynamic for that.)
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16 years ago |
|
Andrew Waterman
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fcdd030cbe
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[sim, xcc] changed cvt/trunc to use GPRs for int args
this way, we don't have to futz with storing integers in recoded
floating-point registers. too bad we lose some decoupling.
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16 years ago |
|
Andrew Waterman
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cbefaf68c7
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[xcc, sim] changed instruction format so imm12 subs for rs2
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16 years ago |
|
Andrew Waterman
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50ec828baf
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[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b
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16 years ago |
|
Andrew Waterman
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2d75bf71bb
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[xcc,sim] implement FP using softfloat
The intersection of the Hauser FP and MIPS FP is implemented.
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16 years ago |
