riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	97a7244371	Avoid dependence on config.h in byteorder.h The runtime check will compile out.	2 years ago
Andrew Waterman	3e44fee398	Don't install private softfloat headers	2 years ago
Andrew Waterman	8feeaf3202	Add include guards to entropy_source.h	2 years ago
Andrew Waterman	238e0ac859	Use "" rather than <> includes in libfdt.h	2 years ago
Andrew Waterman	fb2adef30e	update c++ version to c++2a for CI tests	2 years ago
Andrew Waterman	c96f57e0bb	Fix warning by renaming C++ source to .cc	2 years ago
Andrew Waterman	f205bc4c29	Add missing include	2 years ago
Andrew Waterman	6b89a49838	Merge pull request #1726 from YenHaoChen/pr-dcsr Deprecate dcsr.halt	2 years ago
YenHaoChen	ad86a5fc5c	Deprecate dcsr.halt The debug spec 1.0.0-rc3 deprecates the dcsr.halt and lets the bit become dcsr.nmip. This commit separates the halt variable from the dcsr.nmip and designates it as an internal variable for halt_on_reset (-H). Additionally, this commit removes the notifying comment about the deprecated dcsr.halt in the main loop.	2 years ago
Andrew Waterman	f7d0dba601	Merge pull request #1700 from ved-rivos/ssdbltrp Add Ssdbltrp	2 years ago
Ved Shanbhogue	0797c21001	Add Ssdbltrp	2 years ago
Andrew Waterman	98d2c29e43	Merge pull request #1717 from riscv-software-src/fix-ss-load Loads to shadow-stack pages are allowed	2 years ago
Andrew Waterman	4a2da91667	Merge pull request #1719 from YenHaoChen/pr-encoding Bump encoding.h for dcsr in debug spec 1.0	2 years ago
Andrew Waterman	952b98fd8b	Loads to shadow-stack pages are allowed	2 years ago
YenHaoChen	ec292be4fd	Update encoding.h for pointer masking Rename DCSR_STOPCYCLE to DCSR_STOPCOUNT Rename DCSR_HALT to DCSR_NMIP	2 years ago
Jerry Zhao	1b1a333763	Merge pull request #1714 from abejgonzalez/fix-interactive-insn Fix insn interactive command (catch/print trap, use proper access func)	2 years ago
Jerry Zhao	f2a20b185e	Merge pull request #1715 from abejgonzalez/fix-interactive-vregs Don't print vregs in interactive mode if no V extension exists	2 years ago
abejgonzalez	3947fa0e1c	Don't print vregs if no V exts	2 years ago
abejgonzalez	abb2d55541	Fix insn interactive command (catch/print trap, use proper access func)	2 years ago
Andrew Waterman	ed5f817613	Merge pull request #1709 from abejgonzalez/add-insn-debug-mode-cmds Add insn cmd to interactive debug mode	2 years ago
abejgonzalez	e72fcaa674	Add insn cmds to interactive debug mode	2 years ago
Andrew Waterman	b6498b1596	Merge pull request #1711 from riscv-software-src/zfa-disasm Add disassembly for Zfa extension	2 years ago
Andrew Waterman	6854a911fd	Expand default disassembly ISA	2 years ago
Andrew Waterman	389851ce15	Add disassembly for Zfa extension	2 years ago
Jerry Zhao	d00dfd6615	Merge pull request #1710 from riscv-software-src/fix_debug_ci Fix riscv-tests commit for CI	2 years ago
Jerry Zhao	7f93baf463	Fix riscv-tests commit for CI * https://github.com/riscv-software-src/riscv-tests/pull/567 was merged by squash accidentally, so the reference commit was lost	2 years ago
Jerry Zhao	0c706923b9	Merge pull request #1705 from rpsene/master	2 years ago
Rafael Sene	ef7416ce1d	Fix: Add missing <stdexcept> header for std::logic_error - Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'. Signed-off-by: Rafael Sene <rafael@riscv.org>	2 years ago
Jerry Zhao	f03e97c89f	Merge pull request #1701 from riscv-software-src/zvl_zve Correctly determine vector capability from v/zve/zvl ISA strings, remove --varch	2 years ago
Andrew Waterman	3d4027a2bb	Merge pull request #1704 from riscv-software-src/thread-local-again Fix C/C++ thread-local linkage differently	2 years ago
Andrew Waterman	29da1405c4	Fix C/C++ thread-local linkage differently Just admit Mac OS is broken, so explicitly special-case it. See #1689 and #1703	2 years ago
Jerry Zhao	c790f73ae9	Vector-fp instructions depend on zve, not F/D	2 years ago
Jerry Zhao	67e205c289	Restrict spike to vlen <= 4096	2 years ago
Jerry Zhao	3b6a8fa06e	Remove all --varch parsing	2 years ago
Jerry Zhao	0f4642ee44	Switch to Zvl/Zve parsing from isa_parser, instead of varch	2 years ago
Jerry Zhao	9f5df7f4db	Disallow any vector, not just V, when no __int128 type is present	2 years ago
Jerry Zhao	9ee100f580	Relax require_vector check for misa.V	2 years ago
Jerry Zhao	08d5119d3b	Relax mstatus.vs dependency on full V	2 years ago
Jerry Zhao	a484f6efc5	Relax vector_csr dependency on 'V'	2 years ago
Jerry Zhao	457ea8c0cd	Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve	2 years ago
Jerry Zhao	9925435513	Allow disassembly from implementations that are not full V	2 years ago
Jerry Zhao	24d5693930	Relax has_fs dependency on misa.v isa_parser should already require any Zvef or Zved extensions imply F/D	2 years ago
Jerry Zhao	a3a626b924	Add accessors to isa_parser's VLEN/ELEN	2 years ago
Jerry Zhao	ede537120b	Add Zvl/Zve validation to isa_parser	2 years ago
Jerry Zhao	0408e797b1	Add isa_parser parsing for zvl/zve	2 years ago
Andrew Waterman	6fb4362096	Merge pull request #1702 from riscv-software-src/fix-1696 In isa_parser, move extensionology code before error-checking code	2 years ago
Andrew Waterman	c6cb05ceb7	In isa_parser, move extensionology code before error-checking code Resolves #1696	2 years ago
Andrew Waterman	5e7928a347	Merge pull request #1695 from riscv-software-src/bf16-ops Add several BF16 ops to SoftFloat	2 years ago
Jerry Zhao	a826a4efd2	Merge pull request #1690 from riscv-software-src/fix-warnings Fix a few compile warnings	2 years ago
Andrew Waterman	fe47d091e1	Add several BF16 ops to SoftFloat	2 years ago

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3301 Commits (97a7244371627f37f8086259002e4ed2894f5d0e) All Branches Search

3301 Commits (97a7244371627f37f8086259002e4ed2894f5d0e)

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