If there is no 'mmu-type', we treat it as no mmu implementation
If there is no 'riscv,pmpregions', we treat it as no pmp implementation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
By spec 3.1.6.1 (original behavior)
"x PP is set to the least-privileged supported
mode (U if U-mode is implemented, else M)"
By spec 8.6.4 (h-extension)
"MRET first determines what the new privilege mode will be according to
the values of MPP and MPV in mstatus or mstatush, as encoded in Table 8.8.
MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and
MPIE=1"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
1. support zicntr and zihpm performance extensions
zicntr defines the unprivileged cycle/time/instret
zihpm defines the unprivileged hpmcounter3-31
2. the accessibility are controlled only by
mcounteren/scounteren/hcounteren for access in different privilege
modes
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
We don't actually know that the field in the DTB points at a string
that's less than 256 bytes long, I don't think, so this could probably
cause a buffer overflow on the stack. Anyway, it turns out that
there's no need to copy anything anyway, so let's just update a char**
instead.
Before this change, the MCYCLE CSR was just a proxy for MINSTRET.
Similarly, CYCLE was a proxy for INSTRET. This models a machine where
every instruction takes exactly one cycle to execute.
That's not quite precise enough if you want to do cosimulation: there,
you're going to want to MCYCLE to actually match the behaviour of your
processor (because you need reads from the relevant CSRs to give the
expected result).
This commit splits the two CSRs, leaving the other proxy relationships
unchanged. The code in processor_t::step() which bumps MINSTRET now
bumps MCYCLE by the same amount, maintaining the previous behaviour.
Of course, now a cosimulation environment can update the value of
MCYCLE to fix things up for multi-cycle instructions after they run.
No other functional change. This is preparation for a follow-up
commit, which will split MINSTRET and MCYCLE (to allow cosimulation
environments where the two values might not be equal)
This change makes it possible to faithfully simulate systems which
don't have a CLINT (without adding yet another command line argument
to pass through!).
Without a change like this, lowRISC has been using a local hack in its
Spike fork, where we've just commented out the internals of
clint_t::increment(). This approach is rather cleaner and is hopefully
general enough to use upstream.
This catches silly mistakes like accidentally passing a DTS file when
it should have been a DTB.
Now, you get something like this:
$ /opt/spike/latest/bin/spike --dtb=bogus.dtb -l obj.o
Failed to read DTB from `bogus.dtb': FDT_ERR_BADMAGIC.
This code is identical to make_dtb() which is called in the class
constructor, so I don't think we have to generate/load/parse things
again: we can just use the stuff we made earlier.
These also appear in the disasm subproject (where they make more
sense), which generates Make warnings about duplicate rules.
Before this commit, we were including the code in both libriscv.a and
libdisasm.a:
$ git rev-parse HEAD
c2f30c3330
$ nm libriscv.a | c++filt | grep ' T ' | grep disassemble
nm: libsoftfloat.a: file format not recognized
nm: libfdt.a: file format not recognized
0000000000010b00 T disassembler_t::add_instructions(isa_parser_t*)
00000000000070c0 T disassembler_t::add_insn(disasm_insn_t*)
000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*)
000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*)
0000000000003d30 T disassembler_t::~disassembler_t()
0000000000003d30 T disassembler_t::~disassembler_t()
0000000000003ae0 T disassembler_t::probe_once(insn_t, unsigned long) const
0000000000003cb0 T disassembler_t::disassemble[abi:cxx11](insn_t) const
0000000000003bb0 T disassembler_t::lookup(insn_t) const
$ nm libdisasm.a | c++filt | grep ' T '
0000000000010b00 T disassembler_t::add_instructions(isa_parser_t*)
00000000000070c0 T disassembler_t::add_insn(disasm_insn_t*)
000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*)
000000000001be00 T disassembler_t::disassembler_t(isa_parser_t*)
0000000000003d30 T disassembler_t::~disassembler_t()
0000000000003d30 T disassembler_t::~disassembler_t()
0000000000003ae0 T disassembler_t::probe_once(insn_t, unsigned long) const
0000000000003cb0 T disassembler_t::disassemble[abi:cxx11](insn_t) const
0000000000003bb0 T disassembler_t::lookup(insn_t) const
0000000000000000 T csr_name(int)
Note that this change will have no effect on the contents of
libspike_main.a or libspike_dasm.a: both of these include libriscv.a
and libdisasm.a.
Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.
For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like
rv32imc_Zba_Zbb_Zbs_XZbf_XZbt
and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.
This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.
Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.
Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!
The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.
It's helpful to attempt to disassemble instructions for disabled
extensions, so attempt to do so. Since some extensions conflict
in the opcode space, continue to give higher priorty to explicitly
enabled extensions.
Neel Gala
Andrew Waterman
Chih-Min Chao
Chih-Min Chao
Rupert Swarbrick
John Ingalls
liweiwei
Yueh-Ting (eop) Chen
Tim Newsome