22 Commits (906bbfae48713b9d7256eab37613e5b0ddc08133)

Author SHA1 Message Date
Tim Newsome 127cf78387 DCSR cause was moved, bug debug ROM wasn't updated 10 years ago
Andrew Waterman 78dd5ad00d Add gitignore 10 years ago
Tim Newsome df1f020012 Move sethaltnot and cleardebint. 10 years ago
Tim Newsome 106ece891a New encoding.h for new CSR addresses. 10 years ago
Tim Newsome 8e11417db5 Move cleardebint, per spec. 10 years ago
Tim Newsome 968408423f Change DCSR bits to match spec. 10 years ago
Tim Newsome 060d4ee6c8 Move debug rom link map to the right place. 10 years ago
Tim Newsome 850e745dcf Use fence.i in Debug ROM. 10 years ago
Tim Newsome fdc92ba2c5 Add dret. 10 years ago
Tim Newsome 8e418f9e54 Implement single memory read access. 10 years ago
Tim Newsome 784fea2bbe Exceptions in Debug Mode, stay in Debug Mode. 10 years ago
Tim Newsome 990c6c4809 Have Debug memory kind of working again. 10 years ago
Tim Newsome f7f2623753 Fix race using fence. 10 years ago
Tim Newsome 54bd259cd5 Refactor how we track in-progress operations. 10 years ago
Tim Newsome ffe4998fe5 processor_t unfriends gdbserver_t. 10 years ago
Tim Newsome d999dfc0d4 Add debug_module bus device. 10 years ago
Tim Newsome 191671a201 ROM -> RAM -> ROM, waiting for debug int. 10 years ago
Tim Newsome df640b0cac Jump to the correct (temporary) Debug RAM address. 10 years ago
Tim Newsome 7facb16039 Clean up how Debug ROM is included. 10 years ago
Tim Newsome 6835847f47 Can jump to and execute Debug ROM. 10 years ago
Tim Newsome ddc061f0fb Check in compiled debug ROM. 10 years ago
Tim Newsome ae566cba20 Add debug rom code. 10 years ago