riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Max Chou	85c84f0d27	rvp: Fix packed multiply-subtract operation logic Corrects swapped add/subtract operators in packed 2-way multiply loop. Spec requires (p0 - p1) but implementation computed (p1 - p0). Even elements should add, odd elements should subtract. Fixed instructions: - PM2WSUB.H: P-ext spec - PM2WSUBA.H: P-ext spec Changed: Swapped += and -= for (j & 1) conditional Signed-off-by: Max Chou <max.chou@sifive.com>	2 months ago
Max Chou	4796690c71	rvp: Fix multiply-accumulate result extraction shift amount Corrects shift amount for extracting bits [47:16] from 48-bit multiply-accumulate products. Implementation used 32-bit shift but spec requires 16-bit shift to extract high portion. Fixed instructions: - MHACC.H0: P-ext spec - MHACC.H1: P-ext spec - MHACCSU.H0: P-ext spec - MHACCSU.H1: P-ext spec Changed: mres >> 32 → mres >> 16 Signed-off-by: Max Chou <max.chou@sifive.com>	2 months ago
Chih-Min Chao	36c40b4853	rvp: add missing vxsat updating Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 months ago
Chih-Min Chao	6e0889925b	rvp: fix and simplify behavior Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	38886e3dc7	rvp: refine the sign-extension and extration of mulplication result Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	59b63cf58d	rvp: helper macro doesn't fit some nclip operation also refine writing path to RD Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	8b1ad63088	rvp: do sext32 before writing to rd for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	72a5c14248	rvp: fix the result extraction of multiplication Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	4caf3468b9	rvp: fix shift w/ or w/o saturation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	f720135842	rvp: handle rv64 and rv32 overlap again Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Andrew Waterman	55b4658dbf	Merge pull request #2331 from binno/fix_naming_typo Fix name typo for zvqwbdota8i/zvqwbdota16i extension	1 month ago
Binno	fce96c0b14	Fix name typo for zvqwbdota8i/zvqwbdota16i extension Signed-off-by: Binno <binno.shen@sifive.com>	1 month ago
Andrew Waterman	de0425ad62	Merge pull request #2324 from binno/enable_deleg_bit Switch exception bits by correspond extensions	1 month ago
Andrew Waterman	cb645a0633	Merge pull request #2330 from mslijepc/mslijepc_20260625_ziccrse Add missing Ziccrse extension to disassembler fallback	1 month ago
mslijepc	971b62caa0	Add missing Ziccrse extension to disassembler fallback	1 month ago
Andrew Waterman	27731d158d	Merge pull request #2327 from mslijepc/mslijepc_20260624_ziccamoa Adding Ziccamoa extension to disassembler	1 month ago
mslijepc	f08229cc74	Add missing Ziccamoa extension to disassembler fallback	1 month ago
Andrew Waterman	33c1eb2b25	Merge pull request #2325 from binno/spmp_fixes Apply fixes for SPMP extension	1 month ago
Binno	02d6fc7b4c	Add smpmpdeleg keyword for smpmpdeleg extension Signed-off-by: Binno <binno.shen@sifive.com>	1 month ago
Andrew Waterman	040bdb4c0c	Merge pull request #2322 from EccoTheDolphin/aap-sc/pmp_debug_relaxation relax pmp checks for RWX accesses to debug ROM in debug mode	1 month ago
Anatoly Parshintsev	57af22a174	relax pmp checks for RWX accesses to debug ROM in debug mode Prior this patch it was impossible to enter debug mode when mseccfg.MML was set. The reason is that debug ROM requires both RW and X permissions for debug module to function properly (for example for progbuf execution). This patch relaxes pmp checks and allows unconditional access to debug firmware area whenever the processor is in debug state.	2 months ago
Binno	cf5aa6f8f8	Correct entry index when registering SPMP entry Signed-off-by: Binno <binno.shen@sifive.com>	2 months ago
Binno	c04eb689de	Use SPMP mechanism as satp.mode == Bare with sspmp Signed-off-by: Binno <binno.shen@sifive.com>	2 months ago
Binno	c9c14d2248	Fix error index checking for sspmpen extension Signed-off-by: Binno <binno.shen@sifive.com>	2 months ago
Binno	52ec176103	Switch exception bits by correspond extensions Signed-off-by: Binno <binno.shen@sifive.com>	3 months ago
Andrew Waterman	1280c3ca1e	Merge pull request #2317 from v-efimov/master fixed is_client_connected method in remote_bitbang class	2 months ago
Vladimir Efimov	4e02999d97	fixed is_client_connected method in remote_bitbang class	2 months ago
Andrew Waterman	de82903332	Merge pull request #2313 from riscv-software-src/fix-2312 Fix Ssccfg implementation	2 months ago
Andrew Waterman	623e9029cf	Merge pull request #2315 from riscv-software-src/fix-2314 Disassemble c.ret using correct mnemonic	2 months ago
Andrew Waterman	5bf133772c	Disassemble c.ret using correct mnemonic Fixes #2314 Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 months ago
Andrew Waterman	0b0ac1bd9a	Fix Ssccfg implementation Fib about the address of the counter-config CSRs so that permission checks will succeed in S-mode and so the correct mcounteren bit is checked for the cycle config CSR. Fixes #2312 Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 months ago
Andrew Waterman	3e7bf30da0	Merge pull request #2308 from riscv-software-src/fix-2307 Provide vxsat CSR when P extension is implemented	2 months ago
Andrew Waterman	43c98557f3	Provide vxsat when P extension is implemented Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 months ago
Andrew Waterman	475f94c19d	Abstract away the setting of vxsat Signed-off-by: Andrew Waterman <andrew@sifive.com>	2 months ago
Andrew Waterman	b185929199	Merge pull request #2306 from jameshippisley/sc-pmm-mtval Apply PMM-transformed address to SC access-fault tval	2 months ago
James Robinson	e354c25576	Apply pointer masking to tval on failing SC check_load_reservation's reservable-fault throw was passing the raw rs1 value to tval. Compute the transformed vaddr via generate_access_info and use its transformed_vaddr/effective_virt for the trap, per zpm.adoc pm_csr_hw_apply.	2 months ago
Andrew Waterman	b8ee73addd	Merge pull request #2303 from chihminchao/fix-zvfbfa-conversion zvfbfa: fix contraint for corner cases	2 months ago
Andrew Waterman	5275b9381b	Merge pull request #2304 from chihminchao/rename-dot-product-extenions ext-v: update doc-product extension name	2 months ago
Chih-Min Chao	850f2fb07c	ext-v: update doc-product extension name Use the extension name, defined in spec version 0.2. reference: https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 months ago
Chih-Min Chao	19fce3e336	zvfbfa: fix contraint for corner cases Based on https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc "When altfmt=1 and SEW=8, all vector floating-point instructions become reserved, except for the following, which are redefined to use the BF16 format for any operand that would otherwise have used the FP16 format: vfwcvt.f.x[u].v vfncvt.x[u].f.w vfncvt.rtz.x[u].f.w " Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 months ago
Andrew Waterman	56fd48e786	Merge pull request #2301 from 5265325/fix/dts Emit initrd addresses as 64-bit DT cells	3 months ago
Zhibo Hong	d13c08279b	Emit initrd addresses as 64-bit DT cells The root node advertises #address-cells = <2>, and memory nodes already encode addresses as high/low 32-bit cells. However, linux,initrd-start and linux,initrd-end were emitted as a single cell, which truncates initrd addresses when the memory region is placed above 4 GiB. Emit these chosen properties using the same high/low cell representation so Linux can boot with initrd images located in high memory.	3 months ago
Andrew Waterman	b14b59ed56	Merge pull request #2299 from riscv-software-src/binno-spmp_impl Add SPMP	3 months ago
Andrew Waterman	0348f67cb7	Make PMP lookup more idiomatic	3 months ago
Binno	dfed0035cb	Let PMP and SPMP share the same addr entity Signed-off-by: Binno <binno.shen@sifive.com>	5 months ago
Binno	d9e4cd5396	sspmpswitch -> spmpen Signed-off-by: Binno <binno.shen@sifive.com>	5 months ago
Binno	4850489df5	Implement SPMP extension * Add 'spmp' in isa string parsing for SPMP extension * Add PMP_Entry CSRs of spmp * Implement SPMP matching logic * Update implementation to spec rc5 version	10 months ago
Binno	3cf8ec657d	Update encoding.h (`5b910fd8`) Signed-off-by: Binno <binno.shen@sifive.com>	3 months ago
Andrew Waterman	0bc3241fe1	Merge pull request #2295 from rnax/upstream/rnax/fix-zvdota-zvbdota-fp-exception-flag Add missing set_fp_exceptions in Zvdota/Zvbdota implementations	3 months ago
Max Chou	b50ed90802	zvdota/zvbdota: Add missing set_fp_exceptions for Zvdota/Zvbdota instructions According to the Zvdota/Zvbdota isa spec, RVBNA may raises invalid/overflow exceptions. Add the missing set_fp_exceptions after RVBNA in ZVLDOT_LOOP and ZVBDOT_LOOP to propagate softfloat exception flags to the processor state. Without this, FP exceptions raised during RVBNA accumulation are silently dropped. Signed-off-by: Max Chou <max.chou@sifive.com>	3 months ago

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4117 Commits (85c84f0d2769807aaa38e368772e1763a25a32fb) All Branches Search

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