riscv-isa-sim

4130 Commits

53 Branches

3 Tags

21 MiB

Tree: 84a8cfc49b

Commit Graph

Author	SHA1	Message	Date
Dan Smathers	de8e0588ac	update set_msw/clear_msw/set_mtimer/clear_mtimer Added ifndef to clint addresses instead of hard-coding Added clear_msw and clear mtimer Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests https://github.com/riscv-non-isa/riscv-arch-test/pull/372 Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added. Signed-off-by: Dan Smathers <dan.smathers@seagate.com>	3 years ago
Neel Gala	1b3a5b96f8	adding ports to run F, D and E extension architectural tests on spike	5 years ago
Neel Gala	ccdbfacc9f	adding spike as a target to the arch-test-framework (#630 ) * files and collateral for adding spike as a target to the arch-test-framework * minor typo fix Co-authored-by: Neel Gala <neelgala@incoresemi.com>	6 years ago

Author

SHA1

Message

Date

Dan Smathers

de8e0588ac

update set_msw/clear_msw/set_mtimer/clear_mtimer

Added ifndef to clint addresses instead of hard-coding
Added clear_msw and clear mtimer
Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests
https://github.com/riscv-non-isa/riscv-arch-test/pull/372
Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added.

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

3 years ago

Neel Gala

1b3a5b96f8

adding ports to run F, D and E extension architectural tests on spike

5 years ago

Neel Gala

ccdbfacc9f

adding spike as a target to the arch-test-framework (#630 )

* files and collateral for adding spike as a target to the arch-test-framework

* minor typo fix

Co-authored-by: Neel Gala <neelgala@incoresemi.com>

6 years ago

3 Commits (84a8cfc49b0dca64b64a1b53a48da63c0c1cf7f1)