riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	0125268690	Report misaligned-address exception on failed store-conditionals Previously, the exception would only be raised if the store-conditional would have succeeded.	8 years ago
Palmer Dabbelt	120d2975b3	Merge pull request #247 from heshamelmatary/noisy_until Provide a noisy until interactive command	8 years ago
Hesham Almatary	dc6871efef	Provide a noisy until interactive command This is useful for example when the trace until a PC value needs to be extracted (#246)	8 years ago
Andrew Waterman	f54ff67b56	Set marchid to assigned value 5 https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md TODO: allow Spike users to override marchid/mvendorid/mimpid to mimic their hardware implementations more closely.	8 years ago
Andrew Waterman	1d66556fca	fix disassembly of c.addi4spn Resolves #243	8 years ago
Andrew Waterman	8478969176	Add comment about CSR read side effects	8 years ago
Andrew Waterman	6063149556	For backwards compatibility, reset PMP to permit all accesses	8 years ago
Andrew Waterman	55ef17645d	Add PMP support	8 years ago
takeoverjp	0b8700bb61	Add "--log-cache-miss" option to generate a log of cache miss. (#241 ) * Add "--log-cache-miss" option to generate a log of cache miss. - This option must be used with "--ic" and/or "--dc" options to enable cache simulation. - This option is useful with "-l" option to understand which instruction has caused the cache miss. * Modify log format of cache miss to reduce log size.	8 years ago
Andrew Waterman	6fecdb16d7	Update README	8 years ago
Tim Newsome	def4c5b104	Merge pull request #235 from riscv/sba Fix cut-and-paste bug in 64-bit SBA loads.	8 years ago
Tim Newsome	7de234911f	Fix cut-and-paste bug in 64-bit SBA loads. Fixes #234.	8 years ago
Andrew Waterman	aff796dbf6	Handle spike-dasm inputs with leading 0x correctly	8 years ago
Tim Newsome	176ff23c6f	Add dummy custom debug registers, to test OpenOCD. (#233 )	8 years ago
Andrew Waterman	fad88d8140	Fix several disassembler bugs h/t Shane Lardinois	8 years ago
Andrew Waterman	747a54b103	Add --disable-dtb option to suppress writing the DTB to memory	8 years ago
Andrew Waterman	60235e3816	Make IRQ_COP read-only/undelegable unless coprocessor is present	8 years ago
Andrew Waterman	b6ec196e9e	Instantiate disassembler after max_xlen is known This fixes RVC disassembly. It's done in a way that doesn't break `2cd60b277e`	8 years ago
Andrew Waterman	8a485de092	Don't increment instret immediately after it is written (#231 ) This brings Spike into compliance with this clause in the spec: https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96	8 years ago
Tim Newsome	bed0a54fda	Fix 2 trigger corner cases. (#229 ) 1. When hitting a trigger during a single step, dcsr.cause must reflect the trigger not the step. 2. Also check for triggers on accesses that require a slow path fetch.	8 years ago
Andrew Waterman	1ff2a70ec8	Make sstatus.MXR readable h/t @taoliug	8 years ago
SeungRyeol Lee	2cd60b277e	Fix using the uninitialized disassemble object. (#220 ) This fixes runtime crash when custom extension registers its disassembly.	8 years ago
Andrew Waterman	95487c248a	Refactor and fix LR/SC implementation (#217 ) - Use physical addresses to avoid homonym ambiguity (closes #215) - Yield reservation on store-conditional (`03a5e722fc`) - Don't yield reservation on exceptions (it's no longer required).	8 years ago
Tim Newsome	cc50a327a5	Merge pull request #212 from riscv/hartsel Update debug_defines.h	8 years ago
Tim Newsome	5542d31fcf	Update debug_defines.h Add support for hartselhi parsing, but other parts of the debug code still don't support more than 1024 harts.	8 years ago
Andy Wright	d6fcfdebf6	Put simif_t declaration in its own file. (#209 ) By separating the simif_t declaration from the sim_t declaration, the simif_t declaration no longer depends on fesvr header files. This simplifies compilation of custom sim class implementations that don't depend on fesvr.	8 years ago
Prashanth Mundkur	19efe7d112	Fix install of missed header. (#207 )	8 years ago
Prashanth Mundkur	545911797f	Extract out device-tree generation and compilation into an exported api. (#197 )	8 years ago
Andrew Waterman	d48f107dba	Revert "C.LWSP and C.LDSP with rd=0 are legal instructions" See `01190b6ebe`	8 years ago
Andrew Waterman	d336aee08b	C.LWSP and C.LDSP with rd=0 are legal instructions This mistake derives from an ambiguity in the specification that has since been corrected: `272d038abe`	8 years ago
Andrew Waterman	d2e9a109e8	Fix commit log for serializing instructions Resolves #199	8 years ago
Andrew Waterman	3d016e2765	Only break out of the simulator loop on WFI, not on CSR writes Breaking out of the loop on WFI was intended to let other threads run when the current thread has no work to do. There's no advantage to doing so on CSR writes, and the unintentional change in thread interleaving broke some test programs that relied on short timer periods.	8 years ago
Andrew Waterman	c0172e96bc	When no arguments are passed, print spike help, not fesvr help	8 years ago
Prashanth Mundkur	2dbcb01ca1	Allow querying the mmu configuration chosen during the build. (#191 )	8 years ago
Andrew Waterman	4856220f05	Revert "Fix for issue #183 : No illegal instruction exception for c.sxxi instructions encoded with zero shift amount" This reverts commit `be0555d585`. See #190	8 years ago
Palmer Dabbelt	3242d9b918	Merge pull request #189 from pmundkur/pm-csr-name-api Add an api to get the name for a CSR.	8 years ago
Prashanth Mundkur	fa2aaa3f8a	Add an api to get the name for a CSR.	8 years ago
Andrew Waterman	1da69b975b	Implement Hauser misa.C misalignment proposal (#187 ) See `0472bcdd16` - Reads of xEPC[1] are masked when RVC is disabled - Writes to MISA are suppressed if they would cause a misaligned fetch - Misaligned PCs no longer need to be checked upon fetch	8 years ago
Prashanth Mundkur	ec79312862	Fix the access exception during page-table walks to match the original access type, as specified in the manual. (#185 )	8 years ago
Tim Newsome	0020b3b924	Fix spike-dasm. (#184 ) It had been broken by `90bafe660b`.	8 years ago
Tim Newsome	b4997aa4be	Merge pull request #182 from riscv/reset_bits Implement debug havereset bits	8 years ago
Tim Newsome	90bafe660b	Implement debug havereset bits	8 years ago
Andrew Waterman	403438d609	Merge branch 'deepsrc-b_fix_issue183'	8 years ago
Shubhodeep Roy Choudhury	be0555d585	Fix for issue #183 : No illegal instruction exception for c.sxxi instructions encoded with zero shift amount	8 years ago
Prashanth Mundkur	7e35a2a62f	Fix a bug caused by moving misa into state_t. (#180 ) * Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization. Make state:reset() preserve misa. * Set state.misa to max_isa on reset(). * Idiomatic fix for earlier commit.	8 years ago
Prashanth Mundkur	bdd229b9ea	Move processor.isa to state.misa, since it really belongs there.	8 years ago
Tim Newsome	64947480de	Fix single stepping csrrw instructions (#178 ) This code is still a bit voodoo to me, but now we pass all the tests again. (Stepping was broken by 4299874ad4b07ef457776513a64e5b2397a6a75e.)	8 years ago
Tim Newsome	9d1e10a36e	Merge pull request #177 from riscv/debug_auth Add debug module authentication.	8 years ago
Prashanth Mundkur	4a97a05a6e	Narrow the interface used by the processors and memory to the top-level simulator/htif. This allows the implementation of an alternative top-level simulator class.	8 years ago
Prashanth Mundkur	58aa702359	Fix install of a missed header from debug_rom. The installed header files from the riscv subproject were incomplete, since processor.h includes debug_rom_defines.h, and the latter was not installed. Fix by moving it into riscv/, add it to the riscv subproject header list, which ensures it will get installed. While here, also add a missed dependency of debug_rom on riscv/encoding.h to debug_rom/Makefile.	8 years ago

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975 Commits (833b965679f4502f83c66353bfc07a092cfac9f6) All Branches Search

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