riscv
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riscv-isa-sim
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53 Branches
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19 MiB
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Commit Graph

22 Commits (833b965679f4502f83c66353bfc07a092cfac9f6)

Author SHA1 Message Date
Chih-Min Chao 3d7c842209 rvv: disasm: add v-spec 0.7.1 support
7 years ago
Andrew Waterman 1d66556fca fix disassembly of c.addi4spn
8 years ago
Andrew Waterman fad88d8140 Fix several disassembler bugs
8 years ago
Andrew Waterman 874e55888f Add some missing RVC instructions to disassembler
8 years ago
Kito Cheng 8feec3d0a5 Implement Q extension for disassembler (#153)
9 years ago
Andrew Waterman 4c286ec230 Fix disassembly of c.li 0
9 years ago
Palmer Dabbelt 7f746b7c2f Correct c.li and c.lui disassembly (#118)
9 years ago
Andrew Waterman 115297efff FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
9 years ago
Andrew Waterman 9b6843b58b Remove hret instruction
9 years ago
Andrew Waterman 03b8bad375 Disassemble RVC instructions based on XLEN
10 years ago
neuschaefer 906bbfae48 Minor usability improvements (#48)
10 years ago
Andrew Waterman a9c5b05eca Remove MTIME[CMP]; add RTC device
10 years ago
Andrew Waterman 27e29e69cc Split ERET into URET, SRET, HRET, MRET
10 years ago
Andrew Waterman 575054bc4e Update to hopefully final RVC 1.9 encoding
11 years ago
Andrew Waterman b0f3ed6e3b more work towards RVC 1.8
11 years ago
Andrew Waterman 3fddbcc0a5 work towards rvc 1.8
11 years ago
Andrew Waterman 784e9891af Move towards RVC v1.8
11 years ago
Andrew Waterman bdcb5b297f New RV64C proposal
11 years ago
Andrew Waterman 7f3c072750 Implement RVC draft
11 years ago
Andrew Waterman 49805d2f17 canonicalize assembler pseudo-ops
12 years ago
Andrew Waterman f971129cb6 Disassemble jalr x0, x1, 0 as ret
12 years ago
Andrew Waterman 416c8be88c Support building from within root directory
12 years ago
Scott Beamer fcc557da9d added support for register convention names in debug mode
12 years ago
Andrew Waterman acc42d79e2 fix disassembly of bnez and friends
12 years ago
Andrew Waterman ab14719919 Add fclass.{s|d} instructions
12 years ago
Andrew Waterman 1ea07ef7c5 Fix disassembly of JAL
12 years ago
Christopher Celio 0346522aa6 Disasm now translates xor x0,x0,x0 as a machine-generated bubble ("-").
12 years ago
Andrew Waterman fb3be24671 Eliminate hwacha <-> riscv circular dependence
12 years ago
Andrew Waterman 816893bbe7 Disassemble amoxor
12 years ago
Andrew Waterman e85cb99c5e New RDCYCLE encoding
13 years ago
Andrew Waterman aedcd67ac8 Update to new privileged ISA
13 years ago
Yunsup Lee cb6cfc5f3a refactor disassembler, and add hwacha disassembler
13 years ago
Christopher Celio b9dc340b75 Added commit logging (--enable-commitlog). Also fixed disasm bug.
13 years ago
Andrew Waterman e07148ac53 Implement zany immediates
13 years ago
Andrew Waterman 0642f4db92 Add rd field to JAL; drop J
13 years ago
Andrew Waterman d36c661765 Rename MTFSR/MFFSR to FSSR/FRSR
13 years ago
Andrew Waterman bda232b011 Rename MFTX/MXTF to FMV
13 years ago
Andrew Waterman be9b242d95 Rip out Hwacha for now
13 years ago
Andrew Waterman 0de1489e8a Generate instruction decoder dynamically
13 years ago
Andrew Waterman d237ebbd5c Remove JALR static hints
13 years ago
Andrew Waterman 24cf9ccbb5 update abi register names
13 years ago
Andrew Waterman 8ec519af68 add AUIPC insn; remove RDNPC insn
13 years ago
Andrew Waterman b189b9b128 add load-reserved/store-conditional instructions
13 years ago
Andrew Waterman 28ac3dbd81 add BSD license
13 years ago
Andrew Waterman de5b42e923 change htif to link against libfesvr
13 years ago
Andrew Waterman 01db50f070 new supervisor mode
14 years ago
Yunsup Lee d8a587dedc add disasm functions for vector
14 years ago
Andrew Waterman c12d9358ec fix sltu disassembly
14 years ago
Andrew Waterman 2ddd5fb390 fix compilation for gcc 4.6.1
15 years ago
Yunsup Lee 8ce456c77b fix the fpr abi names
15 years ago