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riscv-isa-sim
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306 Commits
53 Branches
3 Tags
19 MiB
Tree: 826fc1719a
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Commit Graph

16 Commits (826fc1719aaabcf11651b4ede4d98109ad9dc05a)

Author SHA1 Message Date
Albert Ou 826fc1719a Implement "half-baked" half-precision instruction subset for Hwacha
13 years ago
Yunsup Lee 692ba09ef4 include stdexcept
13 years ago
Yunsup Lee 1bcda9195b clarify vxcptsave/vxctkill semantics
13 years ago
Yunsup Lee 74fe66dcec implement vxcptsave/vxcptrestore
13 years ago
Yunsup Lee 787450f4d9 more hwacha supervisor stuff
13 years ago
Yunsup Lee cb6cfc5f3a refactor disassembler, and add hwacha disassembler
13 years ago
Yunsup Lee 9543d241b3 can't execute frsr/fssr on ut
13 years ago
Yunsup Lee 185b0d177d or into control thread's fp exceptions
13 years ago
Yunsup Lee 1057bae0a0 catch trap_illegal_instruction in hwacha
13 years ago
Yunsup Lee 0f140bcde4 add hwacha exception support
13 years ago
Yunsup Lee 1276dd07f7 fix maxvl calc logic
13 years ago
Yunsup Lee da579c14c9 use reset virtual method
13 years ago
Yunsup Lee 38c39525ac use uint32_t for vl
13 years ago
Yunsup Lee 2f1f9a4fbc revamp hwacha; now runs in physical mode
13 years ago
Andrew Waterman b357c97b24 Remove more vector stuff
13 years ago
Andrew Waterman be9b242d95 Rip out Hwacha for now
13 years ago