b3b7ed4c36
Merge pull request #2091 from aap-sc/aap-sc/leakage_fix
Get rid of leaking pointers in examples for custom extension
8 months ago
a191144b7a
Get rid of leaking pointers in examples for custom extention
Building of spike-based simulator with memory sanitizer reports leaking
pointers if custom extension are used. This is because existing
facilities do not have a proper destructor procedure, so the objects
representing custom extentions are leaked. This commit implements
quick-and-dirty fix for the problem.
8 months ago
180c10fe42
csr: fix mseccfg for rv32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
8 months ago
bfe100fbd3
Merge pull request #2088 from ved-rivos/issue_2078
PTE store in s2xlate should use the trap_type instead of type
8 months ago
cfd4930cb6
PTE store in s2xlate should use the trap_type instead of type
8 months ago
f51df5d395
Merge pull request #2077 from riscv-software-src/fix-2076
Prevent div-by-0 when executing Zvbdot instructions with VLEN=0
8 months ago
18bcac3d94
Prevent div-by-0 when executing Zvbdot instructions with VLEN=0
Fixes #2076
8 months ago
545712a6f7
Merge pull request #2074 from riscv-software-src/fix-2073
Allow DEBUG_START to be nonzero again
8 months ago
e80b890ebf
Suppress -Wtype-limits warning
8 months ago
3d85f9af29
Merge pull request #2072 from ved-rivos/issue_2063
Clear SDT in the temporary state variable
8 months ago
743732c3e6
Clear SDT in the temporary state variable
8 months ago
d3be9a4d9d
Merge pull request #2069 from riscv-software-src/fix-zve
Relax VLEN/ELEN checking
8 months ago
1d56b556b5
Relax VLEN/ELEN checking
We should allow ISA strings like rv64gc_zve32f. Per the spec, the
various Zve extensions imply a minimum VLEN, so rv64gc_zve32f
is unambiguously equivalent to rv64gc_zve32f_zvl32b. Similarly,
rv64gc_zve64x, rv64gc_zve64x_zvl64b, and rv64gc_zve64x_zvl32b are
all unambiguously equivalent.
8 months ago
faeae4eada
VLEN is unitless
8 months ago
acac77d59d
No tabs
8 months ago
c3ec317126
Merge pull request #2066 from riscv-software-src/quiet-ci
Quiet the CI logs
8 months ago
7e389e824f
Quiet the CI logs
Send instruction traces to /dev/null to make the CI logs readable.
8 months ago
19409bdfac
Merge pull request #2065 from riscv-software-src/ldot
Add Zvldot extension support
8 months ago
dcef3e5881
Merge pull request #2054 from nadime15/update_vlen_elen
Add VLEN >= ELEN validation check
8 months ago
717a6e275c
Add Zvldot extension support
8 months ago
cfc472e83b
Use f32_add_bulknorm_odd for vfwbdot
8 months ago
cf7d57ef74
Add f32_add_bulknorm_odd routine
Used by Zvldot/Zvbdot
8 months ago
9c190a07c6
Merge pull request #2058 from nadime15/fix-zvfbf-dependency-check
Fix BFloat16 vector extension dependencies and requirements
9 months ago
dcb5f0c784
Remove redundant checks in Zfbfmin and Zvfbfmin validation
9 months ago
715c1597ab
Fix BFloat16 vector extension dependencies
* Enable EXT_INTERNAL_ZFH_MOVE when either Zfbfmin or Zfhmin is enabled
* Change Zvfbfmin to require Zve32f instead of V extension.
* Add proper dependency chain for Zvfbfwma requiring both Zvfbfmin and Zfbfmin.
9 months ago
9a46080b52
Merge pull request #2062 from binno/revert_vstopi_change
Revert "Don't shift enabled bits of interrupt in vstopi csrs"
9 months ago
faeecd8d72
Revert "Don't shift enabled bits of interrupt in vstopi csrs"
This reverts commit e515a8fbcd
9 months ago
eff659cd43
Merge pull request #2056 from binno/remove_shift_in_vstopi
Don't shift enabled bits of interrupt in vstopi csrs
9 months ago
e515a8fbcd
Don't shift enabled bits of interrupt in vstopi csrs
Signed-off-by: Binno <binno.shen@sifive.com>
9 months ago
23ad840e4d
Add VLEN < ELEN validation check
9 months ago
1553a2a896
Merge pull request #2053 from riscv-software-src/fix-2052
Support FLI.H for Zfa && Zvfh && !Zfh
9 months ago
d0c345184f
Support FLI.H for Zfa && Zvfh && !Zfh
Resolves #2052
9 months ago
e17097aaea
Merge pull request #2051 from riscv-software-src/fix-2050
Fix regression introduced by #2050
9 months ago
d951d9bc6a
Fix regression introduced by #2050
Don't assert SEW=8 for fp16 <> int8 conversions.
9 months ago
5da583ee34
Merge pull request #2050 from riscv-software-src/vfp-refactor
Factor out common vector FP prologue
9 months ago
4e4d9f99ee
Factor out rounding-mode validation
9 months ago
3c0db13b52
Factor out common vector FP prologue
9 months ago
2dfd52759b
Merge pull request #2049 from riscv-software-src/vector-cleanup
Minor vector-unit cleanup
9 months ago
d3b3fcba82
Use class member initialization in vector unit
9 months ago
c04d2381d1
Remove dead code in vector unit
9 months ago
dd4d3fbca9
Implement Zvbdot draft
9 months ago
d4568f6693
Merge pull request #2048 from hdinc/patch-1
ns16550.cc : fix handling clear rx/tx FIFO requests.
9 months ago
737787f160
Merge pull request #2046 from ha0lyu/master
fix: check ext_str size when ext = zve*
9 months ago
d62d3075a2
ns16550.cc : fix handling clear rx/tx FIFO requests.
Signed-off-by: hdinc <macellan091@gmail.com>
10 months ago
9950cb3d59
fix: check ext_str size when ext = zve*
`zve*` = "zve{32, 64}{x, f, d}", size of `zve*` must be 6.
Signed-off-by: Hao <58808837+ha0lyu@users.noreply.github.com>
10 months ago
113ef64f67
Merge pull request #2044 from klingaard/klingaard/issue_2038_quad_logging_store_issue
For writes + logging, if len > 8 bytes, break up the memory log
10 months ago
4ecd2e7e79
Merge branch 'master' into klingaard/issue_2038_quad_logging_store_issue
10 months ago
0fa8e0c710
Merge pull request #2040 from mmhus/mmhus/take-sireg-case-out-of-switch
Sireg is not in the sireg_csrs[] list, so needs to be checked outside… #2041
10 months ago
09e4d6d089
Fixed issues with logging
10 months ago
5063dcb8ea
Sireg is not in the sireg_csrs[] list, so needs to be checked outside of the switch-case
10 months ago
Andrew Waterman
Parshintsev Anatoly
Chih-Min Chao
Ved Shanbhogue
Nadime Barhoumi
Binno
Nado15
hdinc
Hao
Knute Lingaard
Knute Lingaard
Muhammad Moiz Hussain