riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	3e44fee398	Don't install private softfloat headers	2 years ago
Andrew Waterman	8feeaf3202	Add include guards to entropy_source.h	2 years ago
Andrew Waterman	238e0ac859	Use "" rather than <> includes in libfdt.h	2 years ago
Andrew Waterman	fb2adef30e	update c++ version to c++2a for CI tests	2 years ago
Andrew Waterman	c96f57e0bb	Fix warning by renaming C++ source to .cc	2 years ago
Andrew Waterman	f205bc4c29	Add missing include	2 years ago
Andrew Waterman	6b89a49838	Merge pull request #1726 from YenHaoChen/pr-dcsr Deprecate dcsr.halt	2 years ago
Binno	4fe12b25db	ssqosid: modify permission check condition for srmcfg The srmcfg csr number is 0x181 which is a S-mode csr The patche uses independant permission check to make the csr available even there is no S-mode	2 years ago
Binno	50c89eaba3	zkr: check extension availability in csr_mseccef permssion check	2 years ago
YenHaoChen	ad86a5fc5c	Deprecate dcsr.halt The debug spec 1.0.0-rc3 deprecates the dcsr.halt and lets the bit become dcsr.nmip. This commit separates the halt variable from the dcsr.nmip and designates it as an internal variable for halt_on_reset (-H). Additionally, this commit removes the notifying comment about the deprecated dcsr.halt in the main loop.	2 years ago
Andrew Waterman	f7d0dba601	Merge pull request #1700 from ved-rivos/ssdbltrp Add Ssdbltrp	2 years ago
Ved Shanbhogue	0797c21001	Add Ssdbltrp	2 years ago
YenHaoChen	707b1f2484	Instantiate vector CSRs only if any_vector_extensions()	2 years ago
YenHaoChen	af90d427af	vector: check extension existence before reading vl	2 years ago
YenHaoChen	67933ec0c3	Check any_vector_extensions() in require_vector_vs	2 years ago
YenHaoChen	cefa747e9a	Check if any vector extensions for vector CSRs	2 years ago
YenHaoChen	eccb557d61	Fix require_vector_vs checking by reverting `66c4853bdc` The require_vector_vs, i.e., sstatus_csr_t::enabled(SSTATUS_VS), was expected to provide has_any_vector() check [1]. Unfortunately, a previous commit [2] made the sstatus_csr_t::enabled(SSTATUS_VS) true without any vector extension. The previous commit [2] was for P-extension, which has been removed from Spike [3]. This commit reverts the commit [2] and corrects require_vector_vs [1]. [1] `a484f6efc5` [2] `66c4853bdc` [3] https://github.com/riscv-software-src/riscv-isa-sim/pull/1660	2 years ago
YenHaoChen	7f8c663886	pointer masking: Implement hstatus.HUPMM (Flush TLB on changing hstatus.HUPMM)	2 years ago
YenHaoChen	69f0c46fe3	refactor: Add specialized hstatus_csr_t	2 years ago
YenHaoChen	c268fb2564	pointer masking: Implement [sh]envcfg.PMM	2 years ago
YenHaoChen	f710dc706b	pointer masking: Implement Smnpm (Flush TLB on changing *envcfg.PMM)	2 years ago
YenHaoChen	faeef6ee14	pointer masking: Let [sh]envcfg.PMM be WARL if with Ssnpm	2 years ago
YenHaoChen	370f741a97	pointer masking: Support _ssnpm to --isa	2 years ago
YenHaoChen	6cc342bcfa	pointer masking: Let menvcfg.PMM be WARL if with Smnpm	2 years ago
YenHaoChen	eea20ae6a2	pointer masking: Support _smnpm to --isa	2 years ago
YenHaoChen	8b5cb0fff2	pointer masking: Let HLVX.* instructions not subject to pointer masking	2 years ago
YenHaoChen	fb761259b3	pointer masking: Let pointer masking not apply when both MPRV and MXR are set	2 years ago
YenHaoChen	a8cc689675	refactor: Add const qualifier to mmu_t::in_mprv()	2 years ago
YenHaoChen	91173cbbc7	pointer masking: Let cache-block management instructions take into account pointer masking	2 years ago
YenHaoChen	42776e6170	pointer masking: Let cache-block zero instruction (cbo.zero) take into account pointer masking	2 years ago
YenHaoChen	5beff7ad19	refactor: Rename parameter addr to original_addr in store_slow_path()	2 years ago
YenHaoChen	68df89718f	pointer masking: performance: Move pointer masking out of store fast path	2 years ago
YenHaoChen	9be6070c56	pointer masking: Let store take into account pointer masking	2 years ago
YenHaoChen	f47782cf9e	refactor: Rename parameter addr to original_addr in load_slow_path()	2 years ago
YenHaoChen	37d06eb8ba	pointer masking: performance: Move pointer masking out of load fast path	2 years ago
YenHaoChen	a15cf880e7	pointer masking: Let load take into account pointer masking	2 years ago
YenHaoChen	dfdd13f529	refactor: Move implementation of generate_access_info() to riscv/mmu.cc	2 years ago
YenHaoChen	c70e0c2a19	refactor: Implement sext(x, pos) macro	2 years ago
YenHaoChen	58defa070e	pointer masking: Let mseccfg.PMM be WARL if with Smmpm	2 years ago
YenHaoChen	436b684ff5	pointer masking: Support _smmpm to --isa	2 years ago
Andrew Waterman	98d2c29e43	Merge pull request #1717 from riscv-software-src/fix-ss-load Loads to shadow-stack pages are allowed	2 years ago
Andrew Waterman	4a2da91667	Merge pull request #1719 from YenHaoChen/pr-encoding Bump encoding.h for dcsr in debug spec 1.0	2 years ago
Andrew Waterman	952b98fd8b	Loads to shadow-stack pages are allowed	2 years ago
YenHaoChen	ec292be4fd	Update encoding.h for pointer masking Rename DCSR_STOPCYCLE to DCSR_STOPCOUNT Rename DCSR_HALT to DCSR_NMIP	2 years ago
Jerry Zhao	1b1a333763	Merge pull request #1714 from abejgonzalez/fix-interactive-insn Fix insn interactive command (catch/print trap, use proper access func)	2 years ago
Jerry Zhao	f2a20b185e	Merge pull request #1715 from abejgonzalez/fix-interactive-vregs Don't print vregs in interactive mode if no V extension exists	2 years ago
abejgonzalez	3947fa0e1c	Don't print vregs if no V exts	2 years ago
abejgonzalez	abb2d55541	Fix insn interactive command (catch/print trap, use proper access func)	2 years ago
Andrew Waterman	ed5f817613	Merge pull request #1709 from abejgonzalez/add-insn-debug-mode-cmds Add insn cmd to interactive debug mode	2 years ago
abejgonzalez	e72fcaa674	Add insn cmds to interactive debug mode	2 years ago

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3530 Commits (79718ed8797147da2219d2f72235f738ded33871) All Branches Search

3530 Commits (79718ed8797147da2219d2f72235f738ded33871)

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