d31b94409c
[xcc,pk,sim,opcodes] added first RVC instruction
15 years ago
98598ca5e2
[sim] fixed multiply-high in rv32
15 years ago
dde934bb5b
[pk,sim] fixed parse-opcodes bug
was causing spurious illegal instruction traps
15 years ago
02166b2691
[opcodes,pk,sim,xcc] fix utidx - add rd
15 years ago
a174f4bfdb
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
15 years ago
fed0e53ae7
[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
15 years ago
9e58791c6b
[opcodes,pk,sim,xcc] add vector mem instructions
15 years ago
c17b57db55
[opcodes,pk,sim,xcc] add stop,utidx instructions
15 years ago
aab3bc1244
[opcodes,pk,sim,xcc] add fence instructions for vector unit
15 years ago
eb6cb4b2ee
[xcc] fixed bug in amo{maxu,minu}.w
15 years ago
99d358e589
[opcodes] minor opcode changes
15 years ago
1598e2964e
[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
15 years ago
3fb2ead615
[xcc,pk,opcodes,sim] updated encoding/insn names
15 years ago
d17ab96ab5
[sim] LWU now illegal in RV32
15 years ago
68591c3c45
[xcc,sim] branches are pc-relative (not pc+4) again
15 years ago
2c3ff5536d
[xcc,opcodes,pk,sim] krste's re-renaming spree
15 years ago
f37be621fe
[xcc,sim,opcodes] removed mtflh/mffl/mffh
in rv32 these will be replaced with loads and stores.
15 years ago
75d9ab427d
[sim,pk] added interrupt-pending field to cause reg
15 years ago
c983d273b2
[sim,xcc,opcodes] added back mtflh.d
15 years ago
28a6b2a350
[opcodes,pk,sim,xcc] synci now bombs whole icache
15 years ago
94dc73b7f1
[xcc,opcodes,pk,sim] cleanup to FP ISA
- Added 5th rounding mode
- Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...)
- merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode
- made MFFL.D and MFFH.D illegal in RV64
15 years ago
ada2fe414b
[sim] added nearest/ties to max magnitude rounding mode
15 years ago
dc1aa62411
[sim] changed divide-by-0 semantics
now it always gives -1, no matter the signedness.
15 years ago
76ee8711f8
[sim,opcodes] add mulhsu instruction
15 years ago
5bae2bf372
[opcodes,pk,sim,xcc] great renumbering of 2011, part deux
15 years ago
f0063c2e8b
[sim, pk, xcc, opcodes] great instruction renaming of 2011
15 years ago
21ce327f5d
[opcodes, sim, xcc] made *w insns illegal in RV32
now generic variants behave differently in RV32 and RV64.
15 years ago
5ddec097b8
[opcodes, pk, sim, xcc] removed nor, normalized macros to addi
15 years ago
db6af47aa9
[sim] fix jalr bug
15 years ago
1313050769
[opcodes,pk,sim,xcc] flip fields to favor little endian
15 years ago
0ea058a5a8
[sim] fixed some compiler warnings
15 years ago
53e36319bc
[sim] cleaned up handling of link register
15 years ago
3ebbeba6d5
[sim] handle integer division overflow
Behavior is now same as GCC's optimizer. Previously, we just crashed :)
16 years ago
259d20a35d
[opcodes, pk, sim, xcc] Tweaked FP encoding
16 years ago
6d443095f9
[opcodes] generate latex and verilog correctly
16 years ago
e59cf7ebfe
[pk] various PK cleanups/speedups
16 years ago
7471eee0ba
[xcc, sim, pk, opcodes] new instruction encoding!
16 years ago
3f144b12ed
[xcc, sim, pk] link register is now x1
16 years ago
68f81d8f48
[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
16 years ago
63844a7558
[sim] removed unnecessary trap in mfcr instruction
16 years ago
5f0b1c3e7b
[sim,xcc] fixed minor bugs related to tp/cr29
16 years ago
78bc7d9885
[pk,sim,xcc] get rid of at register, introduce tp register
16 years ago
2c9a832352
[sim,xcc,pk,opcodes] static rounding modes for FP insns
Now, you can either use the RM in the FSR or specify it in the insn.
(Except for FP->int; no dynamic for that.)
16 years ago
8456c1e923
[pk, sim] added FPU emulation support to proxy kernel
16 years ago
ab928baadb
[sim] made softfloat files C instead of C++
16 years ago
d3cb781e16
[sim] added writeback tracing
16 years ago
9222fb8ab8
[xcc] modified opcodes for better FP decode mapping
16 years ago
9817b7be3d
[opcodes] added code field back to syscall/break
16 years ago
2d58d46c89
[xcc] removed CEXC field from FSR
16 years ago
a359d7b81a
[xcc,sim] eliminated vectored traps
now, the evec register holds the address that all traps vector to,
and the cause register is set with the trap number.
16 years ago
Andrew Waterman
Yunsup Lee
Andrew Waterman