76a4414381
fesvr: Add symbol_elfs field to htif_t
When populated, symbol_elfs are additional elf files that populate the
addr2symbol map in htif
3 years ago
9893d6e939
fesvr: Fix brace style in htif_t::load_program
3 years ago
c97fb920b2
Merge pull request #1273 from riscv-software-src/fix-targargs
Support passing in htif target-arguments through plusargs
3 years ago
1851b45baf
fesvr: fix +signature-granularity opt parsing to be required_arg
3 years ago
0243455b27
fesvr: Add +target-argument= flag to htif parsing
3 years ago
422d297ef0
fesvr: Fix spacing in parse_arguments
3 years ago
6c018d2e56
fesvr: target_args() should return a const
3 years ago
cd0a5dc550
Merge pull request #1272 from sagark/targs-protected
make target_args() protected instead of private to allow subclasses to inject args
3 years ago
34b018ab3a
make target_args() protected instead of private to allow subclasses to inject args
3 years ago
6d6858ce7e
Merge pull request #1268 from riscv-software-src/more-plic-fixes
Don't issue misaligned or non-power-of-2 MMIO accesses
3 years ago
1951f80361
Don't issue misaligned or non-power-of-2 MMIO accesses
@aswaterman explains:
Rather than requiring each MMIO device to support arbitrary sizes and
alignments, decompose MMIO misaligned loads and stores in such a way
as to guarantee their constituent parts are always aligned.
(Specifically, they now always decompose to a sequence of one-byte
accesses.)
This is not a semantic change for main-memory accesses, but it is a
semantic change for I/O devices. It makes them more realistic, in that
most bus standards don't support non-power-of-2-sized accesses.
3 years ago
360e55535d
Fix misaligned accesses to clint's msip regs
Misaligned MMIO is unspecified but this is simple enough.
3 years ago
05f21fa250
Improve plic_context_t initialization style
3 years ago
6ff727a3da
Merge pull request #1251 from plctlab/plct-zc-update-v1.0.3
update support for Zc* to v1.0.3
3 years ago
8c5a857cec
Merge pull request #1267 from scottj97/clint-initialize-mtip
Initialize MTIP at reset
3 years ago
aa10facde0
Merge pull request #1266 from riscv-software-src/fix-o0-compile
Define sim_t::INTERLEAVE so that it can be accessed by reference
3 years ago
7b25014578
Initialize MTIP at reset
Since mtime and mtimecmp both initialize to 0, and "a machine timer
interrupt becomes pending whenever mtime contains a value greater than
or equal to mtimecmp," MTIP should be 1.
Before this change, MTIP would be 0 until the first increment, or
until reading/writing from CLINT regs (since clint_t::load() and
clint_t::store() call increment(0)).
3 years ago
1742648305
Merge pull request #1265 from riscv-software-src/plic-fixes
PLIC and CLINT fixes for heterogeneous harts/discontiguous hart IDs
3 years ago
860a120bf1
Define sim_t::INTERLEAVE so that it can be accessed by reference
std::min takes its arguments by reference, so the arguments need to be
defined. An alternative would have been to force the problematic argument
into being an rvalue (e.g., by adding 0), but this approach seems to me
to be more robust.
This fixes compilation under -O0; see https://github.com/riscv-software-src/riscv-isa-sim/pull/1264#issuecomment-1451114717
@scottj97 I posit that this situation is unusual enough that it shouldn't
motivate us to test -O0 in CI.
3 years ago
74064f8067
Support discontiguous hart IDs in CLINT
This is a large delta because the old implementation baked in multiple
assumptions about the contiguity of hart IDs.
As a side effect, fix implementation for big-endian hosts.
3 years ago
9d3f367203
Fix PLIC on big-endian hosts
3 years ago
2ec72f2a84
Remove unnecessary conditional in plic_t::load
It's safe to overwrite bytes when returning false.
3 years ago
ef1638be6c
Correctly instantiate PLIC contexts for mixed-hart targets
This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.
Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor. In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.
3 years ago
b6d8da39bc
Refactor plic_t and plic_context_t initialization
3 years ago
e09bf027c2
Remove unused plic_context_t::num field
3 years ago
2c9b399f7b
Remove unused plic_t::procs field
3 years ago
d1ae27b7f8
Merge pull request #1259 from WadeGao/perf/wadegao_plic_num_id_words_init_logic_optimization
plic initialization optimize
3 years ago
2badcfb88f
Merge pull request #1246 from riscv-software-src/hartids
Support discontiguous hart IDs in debug module
3 years ago
02515ca125
Merge pull request #1264 from riscv-software-src/fix-interactive-htif
Allow HTIF to make forward progress while running inside interactive mode
3 years ago
e436852d18
Make debug module tolerant of discontiguous hart IDs
The general strategy is to avoid iterating over the ID space.
3 years ago
4acbfe9279
Add cfg_t::max_hartid accessor
The implementation assumes (correctly) that hart IDs are sorted.
Encapsulate that assumption here, rather than scattering it around
the codebase.
3 years ago
4bf371ab1d
Add sim_t::get_harts and sim_t::get_cfg accessors
3 years ago
e4d6a9c1ed
Improve input validation for --hartids flag
Disallow negative hartids, repeated hartids, and empty lists.
3 years ago
b8e562a58c
Use size_t, rather than int, for hartids
They aren't signed quantities.
3 years ago
620e67ebf2
Return periodically from interactive_run and interactive_until
This avoids stalling the HTIF.
3 years ago
3165f365f1
Add ability to partially complete and resume interactive routines
This facility will allow interactive routines to loop without starving
the HTIF.
3 years ago
37d215caf8
Return from sim_t::interactive() when there's no more input
This will allow the HTIF to make progress (after which interactive()
will be invoked again).
3 years ago
b4895800ba
Merge pull request #1261 from viktor-prutyanov/elfloader-assert-remove-1
fesvr: elfloader: replace asserts after open and mmap by exceptions
3 years ago
fe2e84e0ff
fesvr: elfloader: replace asserts after open and mmap by exceptions
Asserts (especially without a message) aren't human readable way of
error reporting. So, replace them by exceptions with messages with
errno string.
3 years ago
8f2994aa7f
optimize `num_ids_word` init logic;
init `max_prio` by initialization-list
3 years ago
b3ef6f7663
Remove redundant RVE related check in cm.mva01s and cm.mvsa01
r1s/r2s > 16 when r1sc/r1sc >2. This will also trigger illegal
instruction exception by CHECK_REG if RVE is enabled
3 years ago
383dbd3822
Add r1s != r2s check for cm.mvsa01
3 years ago
04154f2b30
Update fields name for sreg1/sreg2
3 years ago
72df59bec2
Add support for 'zce' in isa string
3 years ago
0d1a48c0c0
Merge pull request #1256 from scottj97/host_pte_paddr
Rename host_pte_paddr to host_pte_addr
3 years ago
ecf854a158
Rename host_pte_paddr to host_pte_addr
Because it's a host address, it's likely not a physical address at all
-- and we shouldn't care if it is or not.
3 years ago
57e05e97d1
Merge pull request #1254 from WadeGao/fix/unintentional_plic_context_update
fix unintentionally plic context update
3 years ago
750711019e
fix unintentionally plic context update when `val > max_prio` and `offset == CONTEXT_THRESHOLD`
3 years ago
6077cf8880
Merge pull request #1250 from plctlab/plct-misa-fix
Fix writable misa.F/V
3 years ago
32168de8ea
Disable Zvfh when Zfhmin is disabled
3 years ago
Jerry Zhao
Andrew Waterman
Sagar Karandikar
Scott Johnson
Viktor Prutyanov
Wade
Weiwei Li