This is already done for the disassembler (disasm/disasm.cc:882),
but the actual implementations haven't been updated.
A already implies Zaamo,Zalrsc and the other way around (both enabled imply A).
Makes the implementation slightly more correct for when only one standard
extensions is enabled out of the two.
See RISC-V Debug Specification Version 1.0 [6.1.5. Debug Module
Interface Access (`dmi`, at 0x11)], `op` field description:
> 0 (nop): Ignore data and address.
Don’t send anything over the DMI during Update-DR. This operation should
never affect DMI busy or error status.
The algorithm is as follows:
- An instruction-side Bloom filter knows which PPNs might be in the I$
- A store-side Bloom filter knows which PPNs might get store TLB hits
- When refilling the store TLB, search the I-Bloom filter; on a hit,
remove the ITLB entry, rebuild the I-Bloom filter, and flush the I$
- When refilling the ITLB, search the store-Bloom filter; on a hit,
remove the store TLB entry and rebuild the store-Bloom filter
The effect is that any word that can be stored-to cannot be in any I$.
The old scheme (periodically flush I$) was hacky and didn't correctly
respect the in-order fetch rule (i.e. fetches are in-order wrt.
each other, and so they see ordered stores in order).
Section 18.3 says
"The V extension supports all vector load and store instructions
(Section Vector Loads and Stores), except the V extension does not
support EEW=64 for index values when XLEN=32"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Though we use float16_t for vs2 in vfncvtbf16_f_f_w.h and vfncvtbf16_sat_f_f_w.h,
it can pass compilation since they are the same type
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
This commit implements support for the AAMVIRTUAL bit in the abstract memory
access command. When enabled, this bit allows memory accesses to be performed
in virtual address space rather than physical address space.
Changes made:
- Added aamvirtual flag parsing in perform_abstract_memory_access()
- Updated assembly generation to properly handle virtual memory access by
manipulating MSTATUS.MPRV bit
- Added csrrc and csrrw helper functions
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
This commit implements the abstract memory read/write commands in the debug module. The changes include:
- Added support for abstract memory access commands (cmdtype 2) in perform_abstract_command()
- Implemented perform_abstract_memory_access() method to handle memory operations
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
This commit adds support for configuring the number of data registers available
in the debug module. Previously, the debug module had a fixed datasize of 2,
but now users can specify the number of data registers using the --dm-datacount
option when running spike.
The changes include:
- Adding a datacount parameter to debug_module_config_t
- Making dmdata a std::vector instead of a fixed array
- Validating that datacount is between 1 and 12
- Updating the debug module to use the configured datacount
- Adding command-line option to set datacount
- Updating documentation in help output
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
Prior to this commit vectorUnit_t::elt was a bottleneck for vector
instructions performance. This function was not being inlined because
the definition was inside a .cc file. After moving the definition to the
header file I measured the 20-30% increase in performance on random
vector test from CI.
This commits adds basic spike testing using llvm-snippy random code
generator. This initial testing runs spike on random valid code snippets and
checks that it doesn't fail.
Co-authored-by: Ksenia Dobrovolskaya <ksenia.dobrovolskaya@syntacore.com>
Sergei Zimmerman
Evgeniy Naydanov
Andrew Waterman
Andrew Young
Chih-Min Chao
LIU Yu
Binno Shen
Alexander Romanov
Andrew Waterman
Aliaksei Chapyzhenka
Farid Khaydari
Kerim Turak