riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1487 Commits
51 Branches
3 Tags
17 MiB
Tree: 60f7eda71d
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '60f7eda71d'
${ noResults }
Commit Graph

9 Commits (60f7eda71d541e2c708f1b0861ce6ca8800a39f6)

Author SHA1 Message Date
Chih-Min Chao 9bfb43c668
rvb: add xperm.[nbhw] (#629)
5 years ago
Andrew Waterman c9af3ebbcc Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draft
5 years ago
Andrew Waterman c14c1ab21e Remove RV128 fmv.x.q/fmv.q.x instructions from disassembler
5 years ago
Andrew Waterman 236de4dbfa Add Zba/Zbb to disassembler
5 years ago
Chih-Min Chao e88a30c229 disasm: show fench's predecessor and successor
5 years ago
Chih-Min Chao 21458a2710
rvv: index load/store have benn separated into ordered and unordered parts (#611)
5 years ago
Andrew Waterman cab796f546 Start adding B ext to disassembler
6 years ago
Abhinay Kayastha 0748aa4b46 Partially revert removal of .pc.in files; add disasm.pc.in
6 years ago
Andrew Waterman 59d450e586 Separate build of spike and spike-dasm
6 years ago