Because using two booleans gives the impression that there are four
possibilities. Since hideleg is itself masked by mideleg, there are
effectively only three choices, so make that explicit via enum.
Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.
Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>
Error log:
libriscv.a(processor.o): In function `state_t::reset(processor_t*, unsigned long)':
.../_build/../riscv/processor.cc:509: undefined reference to `state_t::num_triggers'
collect2: error: ld returned 1 exit status
Makefile:349: recipe for target 'spike-log-parser' failed
Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>
After excuting vector load/store whole register instructions,
spike would be crashed when excuted the next vector instruction.
Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>
Stringstream is very slow; it's faster to manipulate strings instead.
Also, handle the underscore-dot replacement as a preprocessing step,
rather than doing it redundantly every time.
Optimize the hash functions for RISC-V instruction encodings. This is
only a perf optimization; instructions that don't adhere to RISC-V
standard practice will still disassemble correctly, just more slowly.
We were not properly checking for Machine-level or Supervisor-level
CSR accessibility.
No functional change, but only because all float_csr_t have User-level
permissions today.
Any such instruction should have taken an illegal instruction
exception first.
This would have helped catch #823 where P-extension instructions were
setting vxsat=1 (and mstatus.VS=Dirty) without first checking for
mstatus.VS!=Off.
Any instruction that may write vxsat will take an illegal instruction
exception if mstatus.VS exists and is Off.
In Spike today, mstatus.VS exists iff misa.V=1, which is true iff the
--isa string enables the V extension.
I went through the riscv-p-spec looking for "OV = 1" and added this
behavior to every matching instruction.
See #823 for discussion.
As requested by @marcfedorow:
https://github.com/riscv-software-src/riscv-isa-sim/issues/823#issuecomment-936509476
If mstatus.VS exists (i.e. Vector extension is enabled), it will no
longer be set to Dirty unless the instruction actually sets vxsat.
The mstatus.VS change only affects instructions in the P extension,
since Vector instructions will write other vector state and therefore
still set mstatus.VS=Dirty.
This also affects the commit log. Instructions that don't saturate
will no longer show a write to vxsat.
The VSIE CSR write emulation is broken in latest Spike because
it is allowing only VSSIE bit to be update. This patches fixes
ie_write_mask for VSIE CSR to allow VSTIE, VSSIE, and VSEIE
bits to be updated.
With this patch, we have both Xvisor RISC-V and KVM RISC-V
working again on Spike.
Fixes: 5c1d635c6e ("Convert sie/hie/vsie to csr_t family")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Since this feature is optional and rather niche, don't enable it by
default. This will aid in software development, since it will force
software developed on Spike to be compatible with a much greater set
of vector processors.
To abide by this recent spec change: https://github.com/riscv/riscv-isa-manual/pull/694
Discussed here: 4630011984
This has no functional effect today because the validate_csr() macro
in decode.h has already intercepted and thrown
trap_illegal_instruction() before we reach this code. But I plan to
remove that check next, now that all CSRs are converted to the csr_t
system. After that, this code will matter.
Yueh-Ting (Eop) Chen
Andrew Waterman
Scott Johnson
Elmar Melcher
Mohit Singla
Markku-Juhani O. Saarinen
eric-xtang1008
eric-xtang1008
marcfedorow
liweiwei90
Anup Patel