f2a76d7a3d
misc: fix typo in zawrs incompatible error
6 months ago
3f8e67f69f
feat: support zvkb vector cryptography bitmanip subset extension
This commit gates Zvkb behind Zvkb extension. Previously they were
attached to Zvbb which is Zvkb's superset
6 months ago
a2dc352286
Add Svukte extension support
This adds support for the Svukte extension, which adds support for
address-independent latency of user-mode faults to supervisor addresses.
7 months ago
3f0692d313
decode args for `fcvtmod.w.d` in `zfa` extension
6 months ago
9565a260e9
Add smpmpmt extension
Signed-off-by: Binno <binno.shen@sifive.com>
6 months ago
2ce87219a6
Add Zvfbfa, Zvfofp8min, Zvfofp4min support
7 months ago
7b060d0d86
disasm: show the acquire and release attribute to amo instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
8 months ago
e2e02098a4
ext: add zibi
It implement v0.6 version
reference
https://github.com/riscv/zibi/releases/download/v0.6/zibi.pdf
https://riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
8 months ago
3232ce1b76
Implement Zvflqdot8f
8 months ago
e3dc14a878
Implement Zvfbqdot8f
8 months ago
1d56b556b5
Relax VLEN/ELEN checking
We should allow ISA strings like rv64gc_zve32f. Per the spec, the
various Zve extensions imply a minimum VLEN, so rv64gc_zve32f
is unambiguously equivalent to rv64gc_zve32f_zvl32b. Similarly,
rv64gc_zve64x, rv64gc_zve64x_zvl64b, and rv64gc_zve64x_zvl32b are
all unambiguously equivalent.
8 months ago
faeae4eada
VLEN is unitless
8 months ago
acac77d59d
No tabs
8 months ago
717a6e275c
Add Zvldot extension support
8 months ago
dcb5f0c784
Remove redundant checks in Zfbfmin and Zvfbfmin validation
9 months ago
715c1597ab
Fix BFloat16 vector extension dependencies
* Enable EXT_INTERNAL_ZFH_MOVE when either Zfbfmin or Zfhmin is enabled
* Change Zvfbfmin to require Zve32f instead of V extension.
* Add proper dependency chain for Zvfbfwma requiring both Zvfbfmin and Zfbfmin.
9 months ago
23ad840e4d
Add VLEN < ELEN validation check
9 months ago
dd4d3fbca9
Implement Zvbdot draft
9 months ago
9950cb3d59
fix: check ext_str size when ext = zve*
`zve*` = "zve{32, 64}{x, f, d}", size of `zve*` must be 6.
Signed-off-by: Hao <58808837+ha0lyu@users.noreply.github.com>
10 months ago
cce834e437
Support Ziccid extension
11 months ago
b6a061b683
Support Ziccif extension
11 months ago
d4abc9a71b
AIA: Enable Smcsrind/Sscsrind if supporting Smaia/Ssaia
Smaia/Ssaia allocates indirect CSRs 0x30~0x3f for major interrupt
priorities and 0x70~0xff for external interrupts (only with an IMSIC).
2 years ago
8050278445
AIA: Add isa=..._smaia_ssaia_... option
2 years ago
4764d3c029
Implement Ssccfg & Smcdeleg for spike
Signed-off-by: muhammad.moiz.hussain@semidynamics.com
1 year ago
4d3920b262
Add Svade extension Support
Spike always supports the Svade extension, this is required by the RVA and RVB profiles
1 year ago
b645cc0fba
Explicitly annotate fallthrough cases (-Wextra)
1 year ago
8ccde08b27
Remove unused functions (-Werror)
1 year ago
cfa593d0ea
isa_parser: don't append one char at a time in strtolower
This avoids potential re-alloations as it allocates the result string
upfront.
1 year ago
5ed426bbf4
Add Zvqdotq extension
Not yet frozen, but in a pretty stable state.
See https://github.com/riscv/riscv-dot-product
1 year ago
1e589aa502
Support strict disassembly in disassembler_t
1 year ago
ff771919ec
Updated load/store pair for RV32 to v0.10
- renamed Zcmlsd to Zclsd
- bumped version number
2 years ago
9a641bb03e
Validate Zvl ISA string correctly
See #1810 for explanation of how this can go wrong.
Resolves #1810
2 years ago
6b74bd669d
Validate Zvl ISA string correctly
See #1810 for explanation of how this can go wrong.
Resolves #1810
2 years ago
b47080fea4
Remove --with-priv compile flag
2 years ago
6a1a5db16b
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions
2 years ago
b47d0baab3
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector single-width floating-point fused multiply-add instructions
2 years ago
7f38a503d0
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector widening integer multiply-add instructions
2 years ago
ff62109211
vector: disassemble: Let operand ordering be vd, [vr]s1, vs2 to vector single-width integer multiply-add instructions
2 years ago
9031c7b651
Fix ordering of B single-letter extension
The canonical order is IMAFDQLCBKJTPVH
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
2 years ago
c302e8bd16
Add Smdbltrp
2 years ago
0797c21001
Add Ssdbltrp
2 years ago
370f741a97
pointer masking: Support _ssnpm to --isa
2 years ago
eea20ae6a2
pointer masking: Support _smnpm to --isa
2 years ago
436b684ff5
pointer masking: Support _smmpm to --isa
2 years ago
6854a911fd
Expand default disassembly ISA
2 years ago
389851ce15
Add disassembly for Zfa extension
2 years ago
ef7416ce1d
Fix: Add missing <stdexcept> header for std::logic_error
- Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'.
Signed-off-by: Rafael Sene <rafael@riscv.org>
2 years ago
67e205c289
Restrict spike to vlen <= 4096
2 years ago
457ea8c0cd
Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve
2 years ago
9925435513
Allow disassembly from implementations that are not full V
2 years ago
Alexander Romanov
Alexander Romanov
Andrew Young
LIU Yu
Binno
Aliaksei Chapyzhenka
Chih-Min Chao
Andrew Waterman
Nadime Barhoumi
Nado15
Hao
YenHaoChen
Muhammad Moiz Hussain
Mingzhu Yan
Mahmoud Abumandour
Christian Herber
Jerry Zhao
Ved Shanbhogue
Rafael Sene