riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Tim Newsome	582f4d442e	Refactor build-spike out of test-spike.	3 years ago
Andrew Waterman	9874c17671	Merge pull request #1223 from riscv-software-src/readme Fix supported debug version, use extension names	3 years ago
Tim Newsome	ecda7372d7	Fix supported debug version, use extension names Addresses #1221	3 years ago
Andrew Waterman	3b2e8d53b3	Merge branch 'aap-sc-aap-sc/mem_cfg_corner_cases'	3 years ago
Parshintsev Anatoly	ca1a5fd8f0	improve merge_mem_regions to handle memory region covering the whole 64-bit address space	3 years ago
Parshintsev Anatoly	28eb7aa8be	change mem_cfg_t to accept cases when (base + size) is at 64-bit address space border	3 years ago
Parshintsev Anatoly	f403cb9e54	simplify check_mem_overlap by utilizing get_inclusive_end of mem_cfg_t	3 years ago
Parshintsev Anatoly	fcf61f0008	simplify merge_mem_regions by utilizing get_inclusive_end() of mem_cfg_t this is to properly handle potential 64-bit overflow in (base + size) expression	3 years ago
Parshintsev Anatoly	1e6869c17e	get_inclusive_end implementation for mem_cfg_t The method can simplify proper processing of sitiations when (base + size) overflows 64-bit interger.	3 years ago
Parshintsev Anatoly	e402a8353d	implement get_size() getter for mem_cfg_t object NFT. We also mark `base` and `size` fields as private.	3 years ago
Parshintsev Anatoly	a606da640b	implement get_base() getter for mem_cfg_t object NFC. The intention is for `base` and `size` fields of mem_cfg_t to be private members. This is the fist part of this commit.	3 years ago
Andrew Waterman	3274292415	Merge pull request #1211 from riscv-software-src/speed-up-slow-path Only update histogram when histogramming	3 years ago
Andrew Waterman	571945ca6e	Remove vestigial UNUSED annotation It dates back to when this code was ifdef'd.	3 years ago
Andrew Waterman	3d63b06fae	Only update histogram when histogramming This is worth a 1.4x speedup on the slow path (when not histogramming).	3 years ago
Andrew Waterman	0eec0c9119	Merge pull request #1210 from riscv-software-src/dynamic-dirty-enable Control mmu-dirtying via command line	3 years ago
Jerry Zhao	e7f1798b5d	Remove --enable-dirty compile option	3 years ago
Jerry Zhao	469405129d	Respect --mmu-dirty flag instead of --enable-dirty	3 years ago
Jerry Zhao	d50a0f0022	Add --mmu-dirty runtime flag	3 years ago
Jerry Zhao	c4e7c88728	Add cfg_t field to enable PTE dirtying	3 years ago
Jerry Zhao	044fedabee	Untabify ci-tests/testlib.c	3 years ago
Jerry Zhao	0a59b06f3b	Merge pull request #1209 from riscv-software-src/debugfix Fix debug-mode regression introduced by `20e7f53`	3 years ago
Scott Johnson	b3946f8500	Merge pull request #1207 from YenHaoChen/pr-trap-trigger-common triggers: refactor: add trap_common_t	3 years ago
Jerry Zhao	7334b0180e	Fix debug-mode regression introduced by `20e7f53` - Debug mode should break the processor out of wfi - wfi in debug mode should execute as a nop	3 years ago
Andrew Waterman	4ac904b7c0	Merge pull request #1206 from riscv-software-src/always_misaligned Control whether misaligned accesses are supported via command line	3 years ago
YenHaoChen	89a44eb0a2	triggers: refactor: move mode_match() and textra_match() to private for protected	3 years ago
YenHaoChen	590a36e487	triggers: refactor: create trigger_t::common_match()	3 years ago
YenHaoChen	3b36645442	triggers: refactor: move textra_match() to protected from public	3 years ago
YenHaoChen	247f01691b	triggers: refactor: move textra_match() into detect_trap_match::detect_trap_match()	3 years ago
YenHaoChen	0a45912d60	triggers: refactor: move textra_match() into mcontrol_common_t::detect_memory_access_match()	3 years ago
YenHaoChen	6fd0169b32	triggers: refactor: move detect_trap_match() to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	4cf0ef9c4e	triggers: refactor: create virtual function trap_common_t::simple_match()	3 years ago
YenHaoChen	c0cc59d5c4	triggers: refactor: move get_action() to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	c8ea412319	triggers: refactor: move get_dmode() to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	1517591add	triggers: refactor: move action variable to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	5fa820d323	triggers: refactor: move hit variable to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	1ffeac39c5	triggers: refactor: move dmode variable to trap_common_t from itrigger_t/etrigger_t	3 years ago
YenHaoChen	d9bc868d2c	triggers: refactor: add empty parent trap_common_t class for itrigger_t and etrigger_t	3 years ago
Andrew Waterman	1aac9da38f	Delete --enable-misaligned configure option	3 years ago
Andrew Waterman	b3dfcf1523	Respect --[no-]misaligned command-line flag	3 years ago
Andrew Waterman	a11af65d0e	Add --[no-]misaligned command-line options They don't do anything yet.	3 years ago
Andrew Waterman	8d084dbd09	Pass cfg object to processor_t constructor This reduces boilerplate as we add additional options.	3 years ago
Andrew Waterman	2a95b4e198	Merge pull request #1203 from riscv-software-src/misa-c-read-only Make misa.C read-only	3 years ago
Andrew Waterman	07647a9b53	Merge pull request #1200 from riscv-software-src/mmio_pte Support accessing PTEs through mmio_load/mmio_store	3 years ago
YenHaoChen	9f4a93dbf9	triggers: refactor: add bool etrigger_t::simple_match()	3 years ago
YenHaoChen	007199efdc	triggers: refactor: add bool itrigger_t::simple_match()	3 years ago
Andrew Waterman	96be756b53	Make misa.C read-only This resolves the issue discussed in #1201. Prior to `0adf9307`, clearing misa.C would disable compressed instructions and increase IALIGN to 32. Afterwards, clearing misa.C had essentially no effect because Zca and friends would stay enabled. While AFAICS this isn't technically incorrect, it certainly doesn't follow the principle of least surprise. Instead, remove the feature to toggle misa.C. The effect is that misa.C is 1 iff C is included in the ISA string, and IALIGN is independent of misa.C: specifically, IALIGN is 16 iff Zca is present. (And of course C implies Zca.) Removing the alignment check on misa writes is not a separate commit because these two changes should be made atomically. Not checking the alignment on misa writes goes hand-in-hand with misa.C being read-only.	3 years ago
Andrew Waterman	85f7869bf5	Merge pull request #1205 from riscv-software-src/reservable Add method to probe which memory regions are reservable	3 years ago
Jerry Zhao	43474ddc63	Support pte load/store from mmio regions	3 years ago
Jerry Zhao	25f9028475	Pull pte load/store into methods of mmu_t	3 years ago
Jerry Zhao	c91fe0b0a6	Add method to probe which memory regions are reservable Default reservable regions is the same as before	3 years ago

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2636 Commits (582f4d442ec660affea0d378fad3f8588a7dec16) All Branches Search

2636 Commits (582f4d442ec660affea0d378fad3f8588a7dec16)

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