53222130f6
Add Svadu CSR bit definitions
The Svadu extension adds a HADE field (bit 61) to both
menvcfg and henvcfg. Add the definitions so they can be utilized.
3 years ago
dc280587d6
Add Svadu Extension Parsing to ISA Parser
Make the ISA parser understand the Svadu extension.
3 years ago
471d43a6e3
Merge pull request #1233 from riscv-software-src/pmp64
Support all 64 PMP regions
3 years ago
570eca63d8
Improve PMP number/granularity error messages
3 years ago
42ddc543ed
Perform pmpregions input validation in only one place
No reason to check it both in sim_t::sim_t and in processor_t::set_pmp_num.
3 years ago
a875da544d
Support all 64 PMP registers
3 years ago
a3a663c1e4
Merge pull request #1219 from riscv-software-src/ntriggers
Add --triggers=n to control the number of supported triggers
3 years ago
5fc4374254
Add --triggers flag to select number of triggers
3 years ago
0b379b8be6
Instantiate tdata/tinfo as const csrs when trigger_count == 0
3 years ago
67bbdf5506
Add trigger_count field to cfg_t
3 years ago
7937438882
Merge pull request #1232 from riscv-software-src/jerryz123-patch-1
Add htif_t tohost/fromhost accessors
3 years ago
d02292d928
Add htif_t tohost/fromhost accessors
Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>
3 years ago
a7ac8d85a0
Merge pull request #1230 from gr816ox/patch-2
Add more hint when searched path is wrong
3 years ago
b41209eb36
Add more hint when searched path is wrong
Delete the old branch and pull a new one, because of a wrong force push. Git is not as easy as I think.
Signed-off-by: gr816ox <50945677+gr816ox@users.noreply.github.com>
3 years ago
e4d2458e7e
Merge pull request #1228 from riscv-software-src/ext-limit
Lift artificial limit of 191 extensions; simplify isa_parser_t::extension_enabled
3 years ago
39acd8e2ea
Simplify isa_parser_t::extension_enabled
Now that we guarantee that max_isa and extension_table are synchronized,
we only need to check the latter.
3 years ago
5badd68ae1
Keep max_isa and extension_table in sync in exactly one place
This fixes a bug where --isa=rv64imafdc would fail to set
extension_table['F'] because of the ad hoc manner in which we were
synchronizing max_isa and extension_table.
3 years ago
57ae9e6844
Use more appropriate data structure for extension_table
We know its size at compile time.
3 years ago
830324dcd2
Lift artificial limit of 191 extensions
Add new accessors that accept the isa_extension_t enum.
Retain the original ones that accept unsigned char to avoid churn.
3 years ago
23718cb9b1
Merge pull request #1214 from YenHaoChen/pr-legalize-timing
Add legalize_timing() for tdata1.timing
3 years ago
e3efb15eca
triggers: refactor: use static and remove const for legalize_action()
Since this method does not use 'this', we turn this method into static.
3 years ago
1fc34a04d6
triggers: refactor: use static and remove const for legalize_match()
Since this method no longer use 'this', we turn this method into static.
3 years ago
888ef08c02
triggers: refactor: remove legalization_action()'s dependency on dmode
avoid breaking functionality by reordering statements in tdata1.write()
3 years ago
d61f4a7164
triggers: legalize timing=1(after) for load data trigger
As recommended in the debug spec table "Suggested Trigger Timings", to
avoid the footgun of replaying a load (which may have side effects) when
the breakpoint trap handler returns.
reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1208#issuecomment-1373035906
-----------------------------------------------------------------------
The legalize_timing() depends on select, execution, load, and store,
which are updated in the same function tdata1_write(). As a result,
reordering statements in the tdata1_write() may break the functionality.
Passing those variables as parameters to legalize_timing() does not
solve the problem. Thus, we give the original write value and the masks
of the variables to the legalize_timing(). This makes the legalization
function independent of the updating variables and resolves the issue.
reference: https://github.com/riscv-software-src/riscv-isa-sim/pull/1214
3 years ago
35e229ccfa
Merge pull request #1225 from riscv-software-src/no-threads
Run Spike and HTIF in a single thread, rather than two
3 years ago
469d9c6907
Merge pull request #1224 from riscv-software-src/uart-poll-less-often
For NS16550 UART, poll stdin less often
3 years ago
b8c2b26af8
triggers: refactor: remove an outdated comment
3 years ago
bc53ecdf30
triggers: refactor: add mcontrol_common_t::legalize_timing() function
3 years ago
6b44190063
Run Spike and HTIF in a single thread, rather than two
The two-thread approach was originally motivated by making Spike look
as similar as possible to other HTIF targets. But we can get the same
semantics without threading by running the simulator inside of the HTIF
host's idle loop instead of performing a context switch.
This was motivated by speeding up the simulator on Mac OS (it's worth
around 20% because using pthread condition variables to force strict
alternation is very slow). But I think it also simplifies the control
flow enough to justify it on that basis, too.
3 years ago
d97ad271ee
Merge pull request #1212 from riscv-software-src/debug_smoke
Automatically test that external debug still works.
3 years ago
32cf5bb54a
For NS16550 UART, poll stdin less often
On my Mac Mini, calling `poll()` on stdin takes around 10 us, and we
are invoking it every 20 us or so. Reduce the frequency of polling
by 16x when not actively receiving data, thereby reducing the fraction
of time spent in `poll()` to a trivial amount.
3 years ago
1dc27cfa78
Automatically test that external debug still works.
3 years ago
5e1bdfc496
Use nproc or hw.ncpu instead of -j4 to build spike.
3 years ago
582f4d442e
Refactor build-spike out of test-spike.
3 years ago
9874c17671
Merge pull request #1223 from riscv-software-src/readme
Fix supported debug version, use extension names
3 years ago
ecda7372d7
Fix supported debug version, use extension names
Addresses #1221
3 years ago
3b2e8d53b3
Merge branch 'aap-sc-aap-sc/mem_cfg_corner_cases'
3 years ago
ca1a5fd8f0
improve merge_mem_regions to handle memory region covering the whole 64-bit address space
3 years ago
28eb7aa8be
change mem_cfg_t to accept cases when (base + size) is at 64-bit address space border
3 years ago
f403cb9e54
simplify check_mem_overlap by utilizing get_inclusive_end of mem_cfg_t
3 years ago
fcf61f0008
simplify merge_mem_regions by utilizing get_inclusive_end() of mem_cfg_t
this is to properly handle potential 64-bit overflow in (base + size)
expression
3 years ago
1e6869c17e
get_inclusive_end implementation for mem_cfg_t
The method can simplify proper processing of sitiations when
(base + size) overflows 64-bit interger.
3 years ago
e402a8353d
implement get_size() getter for mem_cfg_t object
NFT. We also mark `base` and `size` fields as private.
3 years ago
a606da640b
implement get_base() getter for mem_cfg_t object
NFC. The intention is for `base` and `size` fields of mem_cfg_t
to be private members. This is the fist part of this commit.
3 years ago
3274292415
Merge pull request #1211 from riscv-software-src/speed-up-slow-path
Only update histogram when histogramming
3 years ago
571945ca6e
Remove vestigial UNUSED annotation
It dates back to when this code was ifdef'd.
3 years ago
3d63b06fae
Only update histogram when histogramming
This is worth a 1.4x speedup on the slow path (when not histogramming).
3 years ago
0eec0c9119
Merge pull request #1210 from riscv-software-src/dynamic-dirty-enable
Control mmu-dirtying via command line
3 years ago
e7f1798b5d
Remove --enable-dirty compile option
3 years ago
469405129d
Respect --mmu-dirty flag instead of --enable-dirty
3 years ago
Aaron Durbin
Andrew Waterman
Jerry Zhao
gr816ox
Scott Johnson
YenHaoChen
Tim Newsome
Parshintsev Anatoly