b9dd2e5d84
Better to raise an illegal-instruction exception upon accessing sireg*
(really vsireg) from VS-mode, while vsiselect holds a value unimplemented.
5 months ago
fd72ee2d3e
Merge pull request #2187 from riscv-software-src/2186-redux
Fix infinite loop due to integer overflow in PMP check
5 months ago
3b9bfa858b
Fix infinite loop due to integer overflow in PMP check
5 months ago
482430178d
Merge pull request #2182 from mmhus/mmhus/reorder_hstateen0_check_smcdeleg
#2082 Reorder hstateen0 check for smcdeleg
5 months ago
9759fef739
Merge pull request #2180 from mslijepc/mslijepc_20251210_softfloat-declaration
softfloat: Add f32_to_i8 and f32_to_ui8 function declarations
5 months ago
6fda58b86a
softfloat: Add f32_to_i8 and f32_to_ui8 function declaration
5 months ago
eef599cc19
#2082 Reorder hstateen0 check for smcdeleg
5 months ago
76e891cab0
Merge pull request #2183 from riscv-software-src/fix-ci
Move CI to MacOS 15
5 months ago
f49a485c02
Move CI to MacOS 15
The MacOS 13 runners have been retired.
5 months ago
abb0d98738
Merge pull request #2166 from Steven-Li-Xiaogang/master
Fix VS-mode check for sireg* (really vsireg*) CSRs
5 months ago
59bf54676e
Merge pull request #2176 from riscv-software-src/fix-flq-fsq-big-endian
Fix Q extension on big-endian targets
5 months ago
57fb2facf3
Fix Q extension on big-endian targets
The previous routines always stored the low-order bits into the
low-order doubleword, which is only correct on little-endian targets.
5 months ago
e04e7f944c
Disable Q extension unless uint128_t is defined
5 months ago
6963ea936a
Merge pull request #2175 from riscv-software-src/improve-mmu-impl
Clean up VA size handling
5 months ago
1bf835816a
Clean up VA size handling
Representing the VA size as a feature set rather than an integer allows
for internal inconsistency and is inelegant.
5 months ago
fd604be778
Merge pull request #2171 from riscv-software-src/fix-svukte
Fix Svukte implementation
5 months ago
62d64ef6bd
Fix Svukte implementation
- Change polarity of svukte_qualified to match ISA spec
- Avoid address dependence of svukte_qualified, per ISA spec
- Move address check to separate routine
5 months ago
3d97c3e1a2
Merge pull request #2153 from chihminchao/enhance-zve
Enhance zve
6 months ago
59c1f33ff5
Merge pull request #2170 from binno/spelp_fix
SPELP field is defined only when S mode is enabled
6 months ago
c6c3d29828
Merge pull request #2168 from riscv-software-src/simplify-opcode-map
Simplify instruction fetch by getting rid of opcode cache
6 months ago
3e9e06b2cd
SPELP field is defined only when S mode is enabled
Signed-off-by: Binno <binno.shen@sifive.com>
6 months ago
b59f916de9
zve: correct the constraint for widening and floating configuraiton
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 months ago
f364814542
zve: correct the requirement for convension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7 months ago
d1e34d021f
zve: some MUL operaiton are unavailable to zve64
Based on section 18.2 in spec
"All Zve* extensions support all vector integer instructions (Section
Vector Integer Arithmetic Instructions), except that the vmulh integer
multiply variants that return the high word of the product (vmulh.vv,
vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not
included for EEW=64 in Zve64*."
"All Zve* extensions support all vector fixed-point arithmetic
instructions (Vector Fixed-Point Arithmetic Instructions), except that
vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
8 months ago
817a4d7800
zve: relax zvfhmin and zvfh
Based on spec
section 18.4
"The Zvfhmin extension depends on the Zve32f extension."
section 18.5,
"The Zvfh extension depends on the Zve32f and Zfhmin extensions."
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
8 months ago
f7616ad7c2
Eliminate the opcode cache
Just bucket the intruction lists, then search them. Simpler and faster.
6 months ago
2ec106b785
Rebuild opcode map whenever ISA/logging changes
This facilitates caching less info in the opcode cache.
6 months ago
bac3747210
Merge pull request #2169 from riscv-software-src/snippy-tests-per-extension
ci: auto-generate per extension snippy tests
6 months ago
0f289394f3
ci: auto-generate per extension snippy tests
This way adding new extension tests is as easy as adding 1 line script
call and it is much harder to leave some instruction untested
6 months ago
6392b9e60d
Merge pull request #2162 from chihminchao/fix-zvfofp4min-contraint
zvfofp4min: fix shared contraint with v[zs]ext
6 months ago
7d49ba7f60
Merge pull request #2163 from chihminchao/fix-double-trap
Fix double trap
6 months ago
46ef2ed8b3
Merge pull request #2167 from riscv-software-src/fix-zawrs-typo
misc: fix typo in zawrs incompatible error
6 months ago
f2a76d7a3d
misc: fix typo in zawrs incompatible error
6 months ago
b4854c1493
Fix VS-mode check for sireg* (really vsireg*) CSRs
6 months ago
755ad71bb7
zvfofp4min: fix shared contraint with v[zs]ext
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 months ago
6d6cc2c525
csr: fix double trap state access
In privilege spec sec 3.1.18
" The Ssdbltrp extension adds the double-trap-enable ( DTE ) field in
menvcfg . When menvcfg.DTE is zero, the implementation behaves as
though Ssdbltrp is not implemented. When Ssdbltrp is not implemented
sstatus.SDT , vsstatus.SDT , and henvcfg.DTE bits are read-only zero."
The change keep the mstatus.sdt unchangedable and always read-as-zero
when menvcfg.dte is cleared
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 months ago
47c1a957c5
csr: move menvcfg in front of mstatus
the following change needs to access menvcfg in mstatus's member
function.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 months ago
65e41ba95a
Merge pull request #2160 from chihminchao/fix-zvfbfmin-with-zvfbfa
zvfbfmin: fix contraint with zvfbfa
6 months ago
12f13d0b85
zvfbfmin: fix contraint with zvfbfa
vfncvtbf16_f_f_w and vfwcvtbf16_f_f_v only depend on
Zvfbf16min but not Zvfbfa
ref:
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc
"
vfwcvtbf16.f.f.v † (only if Zvfbfmin is implemented)
vfncvtbf16.f.f.w † (only if Zvfbfmin is implemented)
The instructions marked with † have the same semantics regardless of altfmt
"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
6 months ago
88edb8b813
Merge pull request #2158 from riscv-software-src/addrmem
Memoize physical address/main-memory map
6 months ago
bbd4eaa8d8
Merge pull request #2157 from riscv-software-src/pmp
Fix PMP checks for misaligned accesses
6 months ago
1ce2d69c28
Memoize physical address/main-memory map
Spike spends a surprising amount of time searching the device map.
6 months ago
6872aabaee
Fix PMP checks for misaligned accesses
`pmp_ok` needs to handle misaligned addresses and non-power-of-2 lengths,
so round them before checking the PMPs.
As an optimization, reduce the number of PMP checks based upon the PMP
granularity.
6 months ago
3767c6e930
Merge pull request #2156 from nadime15/refactor/tighten-extension-validation-zcf
Fix Zcf extension check in misa to require XLEN == 32
6 months ago
080b42d2b0
Fix Zcf extension check in misa to require XLEN == 32
6 months ago
34a42c3807
Merge pull request #2151 from riscv-software-src/speed-up-fetch
Further speed up instruction fetch
6 months ago
fa368ff7ed
Allow TLB hits on LR/SC
6 months ago
de09e78245
Refactor shadow-stack use of xlate_flags_t
6 months ago
2baa7ce02f
Add PTE cache to reduce TLB miss penalty
6 months ago
d545f1336a
Remove unnecessary illegal-instruction checks
All of these are cases where other instructions overlay the reserved
encodings (e.g. C.EBREAK is C.JALR with rs1=x0), so the checks are
redundant.
6 months ago
steven
Andrew Waterman
mslijepc
Muhammad Moiz Hussain
Binno
Chih-Min Chao
Alexander Romanov
Nadime Barhoumi