Prior this patch it was impossible to enter debug mode when mseccfg.MML
was set. The reason is that debug ROM requires both RW and X permissions
for debug module to function properly (for example for progbuf
execution).
This patch relaxes pmp checks and allows unconditional access to debug
firmware area whenever the processor is in debug state.
Fib about the address of the counter-config CSRs so that permission
checks will succeed in S-mode and so the correct mcounteren bit is
checked for the cycle config CSR.
Fixes#2312
Signed-off-by: Andrew Waterman <andrew@sifive.com>
check_load_reservation's reservable-fault throw was passing the raw
rs1 value to *tval. Compute the transformed vaddr via
generate_access_info and use its transformed_vaddr/effective_virt
for the trap, per zpm.adoc pm_csr_hw_apply.
Based on
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc
"When altfmt=1 and SEW=8, all vector floating-point instructions become
reserved, except for the following, which are redefined to use the BF16
format for any operand that would otherwise have used the FP16 format:
vfwcvt.f.x[u].v
vfncvt.x[u].f.w
vfncvt.rtz.x[u].f.w
"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
The root node advertises #address-cells = <2>, and memory nodes already encode addresses as high/low 32-bit cells. However, linux,initrd-start and linux,initrd-end were emitted as a single cell, which truncates initrd addresses when the memory region is placed above 4 GiB.
Emit these chosen properties using the same high/low cell representation so Linux can boot with initrd images located in high memory.
* Add 'spmp' in isa string parsing for SPMP extension
* Add PMP_Entry CSRs of spmp
* Implement SPMP matching logic
* Update implementation to spec rc5 version
According to the Zvdota/Zvbdota isa spec, RVBNA may raises
invalid/overflow exceptions.
Add the missing set_fp_exceptions after RVBNA in ZVLDOT_LOOP and
ZVBDOT_LOOP to propagate softfloat exception flags to the processor
state. Without this, FP exceptions raised during RVBNA accumulation
are silently dropped.
Signed-off-by: Max Chou <max.chou@sifive.com>
The generic compile rules currently rely on the compiler to infer
object and depfile names from the source pathname when -o and -MF
are not passed explicitly.
That works for plain compiler invocations. However, older ccache
versions with CCACHE_BASEDIR can rewrite a symlinked source path to
its target path before deriving the default output names. In that
case, compiling spike_dasm_option_parser.cc may create
option_parser.o and option_parser.d instead of the declared target
filenames, which breaks the build.
Upstream ccache fixed this in v4.12, but older versions remain
common in distribution and CI environments. Pass explicit -o $@ and
matching -MF paths in the generic C, C++, test, program,
install-program, and precompiled-header rules.
This keeps each recipe output aligned with the declared make target
and avoids depending on inferred filenames.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Keep extension_info_t focused on extension enable/imply data
by moving XLEN policy checks back into explicit post-parse validation.
This keeps the table structure simpler while preserving the existing
checks for Zcf, Zclsd, Zilsd, and svukte after implication and
combination rules have settled.
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Replace the long hard-coded extension dispatch chain in isa_parser.cc with
table-driven extension metadata. The table now records the extension name,
the extension bits it enables, direct implied extensions, and simple XLEN
requirements. This makes the parser behavior closer to LLVM, where
extension parsing and implication are represented as data rather than
as a large sequence of adhoc conditionals.
Move MISA single-letter extensions into the same table as multi-letter
extensions. The parser now expands `g` to `imafd`, validates that the base
extension is `i`, `e`, or `g`, and then lets the normal single-letter parsing
loop consume the base extension through the table. This also centralizes
common MISA implications such as `a -> zaamo,zalrsc`, `b -> zba,zbb,zbs`,
`d -> f`, `q -> d,f`, `c -> zca`, and `v -> zve64d,zvl128b`.
Model the Zve implication chain explicitly in the extension table
zve32f -> zve32x, f
zve32x -> zicsr, zvl32b
zve64d -> zve64f, d
zve64f -> zve32f, zve64x
zve64x -> zve32x, zvl64b
v -> zve64d, zvl128b
Keep the Spike-specific Zve state updates out of the table by deriving
VLEN, ELEN, zvf, and zvd from the Zve extension name in a small helper.
Add a separate combine pass for reverse combination rules that reconstruct
combined extension bits from their component bits. This keeps combine logic
separate from forward implication while preserving existing Spike behavior:
zaamo + zalrsc -> A
zba + zbb + zbs -> B
C + D -> Zcd
Zicfiss + Zca -> Zcmop
Retain explicit Spike-specific post-parse checks and derived state where they
remain clearer than table entries, including RV32-only `C/Zce + F -> Zcf`,
`Zfbfmin/Zfhmin -> EXT_INTERNAL_ZFH_MOVE`, incompatibility checks, privilege
mode handling, and VLEN limit validation.
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Chih-Min Chao
Andrew Waterman
Binno
mslijepc
Anatoly Parshintsev
Vladimir Efimov
James Robinson
Zhibo Hong
Max Chou
Christoph Müllner
Jerry Zhang Jian