Sv48x4 is available only if Sv48 is implemented.
Make the same modification for Sv39x4, too. Technically, we do not
need this check, since RV64 implementations of the hypervisor extension
require Sv39. But the code looks more symmetrical this way, and it will
sidestep a pitfall if we ever have sPMP-only hypervisors.
'The instructions operate as if EEW=SEW.EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte should take sew into acount when vstart != 0
The main motivation for this is that we want to move the ISA parsing
logic to run before we even construct a simulator. That's probably a
bit nicer if we don't depend on the processor header.
It also means that we can stop depending on processor.h in disasm.cc
or spike_log_parser.cc (both through disasm.h), which feels a bit
cleaner: making sense of an instruction trace shouldn't really require
knowledge of the internal state of a processor.
This commit defines a "cfg_t" structure, which currently just holds
the initrd address range. It will be augmented in future commits to
hold other configuration arguments as well.
To represent a configuration argument, we define an arg_t base class.
This holds a current value, together with a flag that tells us whether
the value has been updated from the default. The idea is that in
future we're going to use that flag when reading a DTB file: if an
argument has actually been specified on the command line, we need to
take it into account; if not, we can ignore the default and use the
DTB file's supplied value.
dirty() almost never changes any state. Reading the old dirtiness state
and comparing is much faster than writing, so gate the write.
This commit does introduce a benign functional change: it eliminates
logging messages for e.g. FS changing from Dirty to Dirty.
Eliminate calls to base_status_csr_t::enabled() so that the various
read() calls can be inlined. Doing so also removes a redundant check of
sstatus_write_mask.
Schedule the most common exit path first.
Since many instructions are only conditionally legal, their
implementations need to query misa (or isa). Since reading
misa is therefore on the critical path, make sure it's inlined.
Making misa_csr_t a final class sidesteps the need for a vtable
lookup when calling read().
This is a minor change, turning processor_t from a child class of
isa_parser_t into a class that contains an isa_parser_t as a field.
The point is that it is a step toward separating out
"configuration" (and ISA string parsing) from processor state. This
should be helpful for rejigging things so that we construct more from
a supplied device tree.
Andrew Waterman
Mark Fedorov
Alenkruth Murali
Scott Johnson
liweiwei90
Rupert Swarbrick
Tim Newsome
Weiwei Li
Neel Gala