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riscv-isa-sim
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21 MiB
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968 Commits (48fe0c484d50073bd5d12bdb7fef5b7ea257e006)
 

Author SHA1 Message Date
Megan Wachs 12b772563a debug: Move things around, but addresses now conflict with ROM.
9 years ago
Megan Wachs 6480784223 debug: consider COMMAND.transfer bit, and implment HARTINFO
9 years ago
Megan Wachs bbbe41e636 debug: Compiles again with new debug_defines.h file, but not tested.
9 years ago
Megan Wachs 0d803176c9 debug: bump the debug_defines to match spec
9 years ago
Megan Wachs 84e1ac19ed Merge remote-tracking branch 'origin/priv-1.10' into HEAD
9 years ago
Andrew Waterman d6fce45976 Implement new FP encoding
9 years ago
Andrew Waterman 5f494a22db Implement vectored interrupt proposal
9 years ago
Andrew Waterman 1132fdf4f0 Add --enable-misaligned option for misaligned ld/st support
9 years ago
Yunsup Lee f2e8eb28cc update encoding.h to get PMP updates
9 years ago
Andrew Waterman 32f8b0bbb8 Update LICENSE copyright date
9 years ago
Wesley W. Terpstra b04dfe31de fdt: move interrupt controller into its own node
10 years ago
Andrew Waterman 7b396b51a6 Set badaddr=0 on illegal instruction traps
10 years ago
Andrew Waterman 8f4fb411b0 On EBREAK, set badaddr to pc
10 years ago
Andrew Waterman a80c695b19 Separate page faults from physical memory access exceptions
10 years ago
Andrew Waterman 1fa2174178 Default to 2 GiB of memory
10 years ago
Andrew Waterman e83a032060 Require little-endian host
10 years ago
Wesley W. Terpstra 46f1423c65 riscv: replace rtc device with a real clint implementation
10 years ago
Wesley W. Terpstra 693fc45eb8 sim: declare cores as interrupt-controllers for clint
10 years ago
Wesley W. Terpstra 212d5198cf bootrom: set a0 to hartid and a1 to dtb before boot
10 years ago
Wesley W. Terpstra 0647cce541 configstring: rename variables to dts
10 years ago
Wesley W. Terpstra 4c80b12b1a riscv: remove dependency on num_cores
10 years ago
Wesley W. Terpstra f7a7557273 bootrom: include compiled dtb
10 years ago
Wesley W. Terpstra 4198bc7c62 sim: create DTS instead of config string
10 years ago
Wesley W. Terpstra fcd0f3ab3b sim: define emulated CPU clock rate to be 1GHz
10 years ago
Wesley W. Terpstra c71db7787b autoconf: put location of 'dtc' into config.h
10 years ago
Palmer Dabbelt 773fab34d4 spec bump
10 years ago
Andrew Waterman ee80f2851a PUM -> SUM; expose MXR to S-mode
10 years ago
Andrew Waterman 5ed1c1f9de Simplify interrupt-stack discipline
10 years ago
Andrew Waterman 17e3ef9618 Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
10 years ago
Andrew Waterman 3c8dafeef0 Don't overload illegal instruction trap in interactive code
10 years ago
Andrew Waterman cbaa72d24c Sv57 and Sv64 are not spec'd yet
10 years ago
Andrew Waterman 6db0707687 New counter enable scheme
10 years ago
Tim Newsome ab8a5631c3 Update bits to latest spec.
10 years ago
Tim Newsome 5a9e289624 Implement halt request.
10 years ago
Tim Newsome 21fb735d62 Improve debug performance.
10 years ago
Tim Newsome 0e848d2f43 Don't waste time spinning in place in debug mode
10 years ago
Andrew Waterman 13639b9c45 serialize simulator on wfi
10 years ago
Andrew Waterman b47e8c0a19 Take M-mode interrupts over S-mode interrupts
10 years ago
Andrew Waterman f478eef851 permit MMIO loads to MSIP bit
10 years ago
Andrew Waterman 67cd71d9ec Make HW setting of PTE A/D bits optional (by configure arg)
10 years ago
Andrew Waterman eace559960 Spike uarch needs TLB flush after SPTBR write
10 years ago
Tim Newsome e36bacd9bc Compress log output of jump-to-self loops.
10 years ago
Tim Newsome 8c19757cf5 Remove noisy debugs.
10 years ago
Tim Newsome 8dd673b744 Set cmderr when data is accessed while busy.
10 years ago
Tim Newsome f88504000a Implement autoexec. DMI op 2 is just write now.
10 years ago
Tim Newsome 4df7f6d279 Implement resume (untested).
10 years ago
Andrew Waterman d503765577 sfence.vm -> sfence.vma
10 years ago
Tim Newsome 294a0572c4 Implement program buffer preexec/postexec.
10 years ago
Tim Newsome ae67cde583 dbus -> dmi
10 years ago
Tim Newsome 1a62370146 Abstract register read mostly working.
10 years ago