Maintain a shadow structure of isa_parser_t::extension_table,
processor_t::extension_enable_table, which tracks whether such
extensions have been dynamically enabled or disabled.
Sanity-check that `extension_enabled_const` honors its contract.
The use of `mutable` is somewhat unfortunate, but we think it's
acceptable here because the only thing that's mutating is this
sanity-checking code, not visible to any consumer of this class.
!dtb_enabled will now result in the following behavior:
* sim_t.dts and sim_t.dtb will be empty
* the dtb_file passed to sim_t will be ignored
* The default bootrom will not be instantiated
* Bus devices normally configured by parsing the dtb will not be added
This includes the CLINT/PLIC/UART
Before 3b26740, the reset was necessary because sim_t::get_dts would be
called before sim_t::make_dtb was called in reset(). This is no longer
necessary since now `make_dtb` is called in the constructor of sim_t
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
The addition of Svadu support and removal of --mmu-dirty
command line flag results in the dirty_enabled configuration state
no longer being used. Remove the remnants of this state.
The Svadu (https://github.com/riscv/riscv-svadu) extension updates
the A/D bits of PTEs:
1. In S/HS mode when menvcfg.hade=1
2. In G-stage page tables when menvcfg.hade=1
3. In VS mode when henvcfg.hade=1
To enable this behavior the 'svadu' ISA string is needed.
This newly added behavior supplants the --mmu-dirty flag. However,
that flag is not yet removed.
Add in the support for the HADE fields in menvcfg and henvcfg
based off of the svadu ISA string. This only allows for the writable
HADE bits being exposed when the svadu ISA string is employed. No
other behavior is implemented.
Andrew Waterman
Weiwei Li
Jerry Zhao
Neel Gala
Philipp Tomsich
Scott Johnson
YenHaoChen
Aaron Durbin