riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	3177a7c5a6	Merge pull request #129 from riscv/q-extension Implement Q extension	9 years ago
Andrew Waterman	85c40db208	Implement Q extension	9 years ago
Tim Newsome	58b6c187df	Merge pull request #128 from riscv/reset Fix debug reset.	9 years ago
Andrew Waterman	bd85811c35	Update SoftFloat	9 years ago
Tim Newsome	def8b3e05d	Actually let hartreset be set.	9 years ago
Tim Newsome	526d3997e6	Fix debug reset. ndmreset now resets all harts (instead of just the current hart), and hartreset resets the selected hart (instead of being ignored).	9 years ago
Tim Newsome	b86f2a51f5	Fix corner case in repeated execution (#127 ) Specifically, don't print out the execution count if the same instruction is executed by different harts.	9 years ago
Tim Newsome	c471f5d84e	Fix comment typo. (#126 )	9 years ago
Tim Newsome	8969a85513	Merge pull request #123 from riscv/debug_interrupts Don't take interrupts while in Debug Mode.	9 years ago
Tim Newsome	fb1f3f7ca9	Don't take interrupts while in Debug Mode.	9 years ago
Tim Newsome	111dce1919	Merge pull request #121 from riscv/debug_store Add a nice debug printf for debug_module_t::store	9 years ago
Tim Newsome	b5bbd05923	Add a nice debug printf for debug_module_t::store	9 years ago
Tim Newsome	3151df24e5	Merge pull request #119 from riscv/quiet Turn off debug module debug printfs.	9 years ago
Tim Newsome	2e47be027c	Turn off debug module debug printfs. Nobody wants to see all that, and if they do they should recompile.	9 years ago
Palmer Dabbelt	7f746b7c2f	Correct c.li and c.lui disassembly (#118 ) I currently get this disassembly 00004881 jr a7 but if I understand that's incorrect and I want 00004881 li a7, 0 If I'm reading the ISA manual correctly, the disassembler was just wrong here.	9 years ago
Tim Newsome	96218b1cdc	Merge pull request #117 from riscv/multicore_debug Fix multicore debug.	9 years ago
Tim Newsome	4f8b6a6948	Fix multicore debug. In an older implementation I was thinking of having different entry points for different harts, but that's no longer true. Also get rid of a bunch of trailing whitespace.	9 years ago
Andrew Waterman	a327416eac	Remove reference to H-mode in ECALL	9 years ago
Palmer Dabbelt	3a4e89322a	Merge pull request #113 from riscv/debug_readme Update README to use --rbb-port	9 years ago
Tim Newsome	1e2518d415	Support 64-bit start PCs in reset vector.	9 years ago
Tim Newsome	c354cfe89c	Update README to use --rbb-port	9 years ago
Tim Newsome	f65e7e585f	Merge pull request #112 from riscv/autoexecwrite Return success on writes to abstractauto	9 years ago
Tim Newsome	071610e2b2	Return success on writes to abstractauto This bug was exposed by newer OpenOCD which actually checks the result.	9 years ago
Tim Newsome	5307bcf478	Merge pull request #110 from riscv/debug_rom_build `make clean && make` works again in debug_rom	9 years ago
Tim Newsome	c4cb4a5de9	Merge pull request #111 from riscv/dtm_reset_error Reset to "success" instead of "error."	9 years ago
Tim Newsome	1a904654f1	Reset to "success" instead of "error." OpenOCD actually checks this initial value now, and there's no reason for it to indicate error.	9 years ago
Tim Newsome	290115aeac	`make clean && make` works again in debug_rom	9 years ago
Andrew Waterman	3e92055f83	Forbid S-mode execution from user memory `285c81746f`	9 years ago
Palmer Dabbelt	ea6768d281	Merge pull request #108 from riscv/dtc-error Configure should fail if device-tree-compiler is not installed	9 years ago
Andrew Waterman	1e80c6d236	Configure should fail if device-tree-compiler is not installed Fixes #107	9 years ago
Andrew Waterman	ba28ea06d5	minNum -> minimumNumber	9 years ago
Palmer Dabbelt	e89fade1a7	Merge pull request #104 from riscv/disable-werror Disable -Werror when building	9 years ago
Palmer Dabbelt	40d2eabbba	Disable -Werror when building This has a tendency to blow up on other platforms.	9 years ago
Palmer Dabbelt	b3caeee985	Merge remote-tracking branch 'origin/priv-1.10'	9 years ago
Palmer Dabbelt	a1f754b2f0	Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10	9 years ago
Palmer Dabbelt	9b539c8f0e	Better error message when doing DMI operations and we're busy	9 years ago
Megan Wachs	a5c5d0ccf2	debug: whitespace errors	9 years ago
Megan Wachs	f14da97c12	Merge branch 'debug-0.13' into HEAD	9 years ago
Andrew Waterman	e465de145c	Make C.LI/C.LUI trapping behavior match spec	9 years ago
Andrew Waterman	12926c7ad6	UXL=SXL=MXL `326bec83de`	9 years ago
Andrew Waterman	8a428c769b	Trap superpage PTEs when PPN LSBs are set	9 years ago
Kito Cheng	68f1a893ec	Add missing include for devices.h - https://github.com/riscv/riscv-tools/issues/69	9 years ago
Andrew Waterman	63c98b41ae	Fix segfault when accessing bad memory addresses	9 years ago
Andrew Waterman	75f2a05df9	Set default entry point from ELF	9 years ago
Andrew Waterman	4859971a88	Add option to set start pc	9 years ago
Andrew Waterman	abb7dddfdf	Support more flexible main memory allocation	9 years ago
Andrew Waterman	1d2892407f	Store both host & target address in soft TLB	9 years ago
Palmer Dabbelt	1eee4de6b3	Merge pull request #96 from riscv/ndmreset Updates to match the latest debug spec	9 years ago
Palmer Dabbelt	588fc79f17	Remove a debugging printf	9 years ago
Palmer Dabbelt	2f346fd7e0	Don't spin on the remote bitbang reads	9 years ago

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